Differences

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--- language:langs:spec [2023/01/06 09:33]
rajit [Timing constraints]
+++ language:langs:spec [2024/02/02 06:12] (current)
rajit
@@ Line 37: / Line 37: @@
 The directive ''rand_init'' is used to let the simulator know that a signal might be undefined on power-up, but will initialize to either 0 or 1 at random. The directive ''hazard'' is used to let the simulator know that a particular signal can have a switching hazard.
-==== Timing constraints ====
+==== Timing directives ====
-Timing constraints in ACT are specified using timing forks. Timing forks are used to specify a point of divergence constraint. The constraint
+There are two types of timing directives: constraints, and tick specifiers on timing edges.
+=== Tick specifiers ===
+Asynchronous circuits oscillate, and each oscillation can be viewed as an iteration of the circuit. For [[asic:timing:graph|timing analysis]], it is important to indicate connections from one iteration to the next---i.e. when a signal transition from the current indication leads to a transition from the next iteration. Such directives can be computed during logic synthesis, and ACT expects all logic synthesis tools to emit these directives along with the gate-level implementation.
+<code act>
+spec {
+   timing a+ -> c-
+ }
+</code>
+This directive says that ''a+'' on a particular iteration directly leads to ''c-'' in the next iteration. (Sometimes these are called //ticked// edges in the timing graph.((S.M. Burns and A.J. Martin. Performance Analysis and Optimization of Asynchronous Circuits. Proc. ARVLSI, 1991.))((Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018.))
+=== Timing constraints ===
+Timing constraints in ACT are specified using [[asic:timing:forks|timing forks]]. Timing forks are used to specify a point of divergence relative timing constraint. The constraint
 <code act>
 spec {
@@ Line 54: / Line 68: @@
 This specifies that the timing fork has a margin of 15 delay units. The conversion from delay units to actual time uses the ''prs2net.conf'' [[config:netlist#Device generation and parameters|configuration parameter]] ''net.delay''.
-Asynchronous circuits oscillate, and each oscillation can be viewed as an iteration of the circuit. For timing analysis, it is important to indicate connections from one iteration to the next---i.e. when a signal transition from the current indication leads to a transition from the next iteration. Such directives can be computed during logic synthesis, and ACT expects all logic synthesis tools to emit these directives along with the gate-level implementation.
+If a circuit violates a timing fork, that is an error that is flagged by the ACT simulation tools. During the implementation flow, these timing forks have to be checked. If they are violated, then the circuit must be adjusted to ensure that they are satisfied. There are two ways to satisfy a fork: (i) make the slow path faster; or (ii) make the fast path slower. Adding delays to a fast path is one way to satisfy a timing fork, but that may result in slowing down the circuit. Hence, the default optimizations will attempt to make the slow path faster.
+In some cases, a user may want the circuit synthesis and optimization tools to insert the appropriately sized delay line to make the fast path slower. In other words, rather than manually specifying the delay line, a timing fork can be specified where the implementation flow should just add the appropriately sized, technology-dependent delay line. In such cases, a timing fork can be specified as follows:
 <code act>
 spec {
-   timing a+ -> c-
+  timing a+ : b- << [15] c+
- }
+}
 </code>
-This directive says that ''a+'' on a particular iteration directly leads to ''c-'' in the next iteration. (Sometimes these are called //ticked// edges in the timing graph.((S.M. Burns and A.J. Martin. Performance Analysis and Optimization of Asynchronous Circuits. Proc. ARVLSI, 1991.))((Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018.))
+This has the same meaning as the earlier fork, except that the tools are provided with a hint that says that it is okay to add delays to correct any violations of this fork.
 Finally, timing forks may relate transitions from adjacent iterations.