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language:langs:start [2022/06/23 17:34] rajit |
language:langs:start [2022/06/29 16:20] rajit [Selecting sub-language level] |
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===== Sub-languages to specify circuits ===== | ===== Sub-languages to specify circuits ===== | ||
+ | |||
+ | ACT has the following four sub-languages that are used to specify circuits: | ||
* [[chp|Communicating hardware processes]]: | * [[chp|Communicating hardware processes]]: | ||
* [[dflow|Dataflow]]: | * [[dflow|Dataflow]]: | ||
- | * [[hse|Handshaking expansions]]: | + | * [[hse|Handshaking expansions]]: |
* [[prs|Production rules]]: gate-level and transistor-level circuit specification | * [[prs|Production rules]]: gate-level and transistor-level circuit specification | ||
- | | + | |
+ | |||
+ | When simulating a design or translating the circuit to an implementation, | ||
+ | |||
+ | The CHP sub-language is used to describe the circuits using a programming notation. The HSE sub-language operates on Boolean-valued variables, and has syntax similar to the CHP block. A process can have at most one CHP block and at most one HSE block; if multiple blocks of the same type are detected, an error will be flagged. | ||
+ | |||
+ | The dataflow sub-language can be used to specify computations as a static dataflow graph. The PRS sub-language can be used to specify gates as well as transistor-level implementations of circuits. These blocks can be repeated in a process, and the result is the concurrent composition of the blocks. | ||
+ | |||
+ | When translating circuits from one level of abstraction to another (especially going down to production rules), it may be helpful to add additional levels of design hierarchy (e.g. by instantiating standard gates). To support this, ACT includes a refinement body. | ||
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+ | | ||
+ | |||
+ | The refinement | ||
===== Auxillary sub-languages ===== | ===== Auxillary sub-languages ===== | ||
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* [[spec|Specifications]] | * [[spec|Specifications]] | ||
+ | ===== Selecting sub-language level ===== | ||
+ | |||
+ | There are four possible levels of detail at which to model a circuit component: | ||
+ | * CHP, where channels and full expression syntax is permitted | ||
+ | * HSE, where sequencing can be specified, but all variables are Boolean-valued | ||
+ | * PRS, which corresponds to individual pull-up and pull-down networks (gates) | ||
+ | * device, which corresponds to the transistor-level implementation of the gates. The device level doesn' | ||
+ | |||
+ | A configuration file can be specified that selects the level of detail for a process | ||
+ | |||
+ | < | ||
+ | begin level | ||
+ | # valid strings are " | ||
+ | | ||
+ | end | ||
+ | </ | ||
+ | This specifies the default level selected for every process. (Dataflow is treated as fine-grained parallel CHP.) | ||
+ | |||
+ | < | ||
+ | begin level | ||
+ | begin types | ||
+ | # chp process model | ||
+ | | ||
+ | # prs process model | ||
+ | | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | This specifies that the particular process names should be modeled at the specified level of abstraction. | ||