The ACT VLSI design tools

actsim - [Manipulating internal variables]

rajit (rajit@undisclosed.example.com) — 2026-05-03T17:00:48+00:00

Actsim: an ACT simulator To run actsim, you need to select the ACT file to simulate and the top-level process for your design: % actsim file.act process actsim> A simple example The following ACT file is a CHP example that sends three integers on an output channel, and connects that process to one that simply receives an integer and displays it to the screen.

start - [Session 2: From Behavior to gates]

rajit (rajit@undisclosed.example.com) — 2026-05-01T12:46:02+00:00

ASYNC 2026 Summer School The 3rd edition of the ASYNC Summer school will be co-located directly before the conference (June 1-2 2026) as a hybrid event at DTU in Lyngby, Denmark. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools.

migrate - [Loops]

rajit (rajit@undisclosed.example.com) — 2026-04-19T13:55:16+00:00

Migration guide If you have previously used ACT (versions from 2006 to 2018), there are a few minor changes that clean up the language and make the syntax more consistent. There are also some new features that you might find helpful that simplify describing circuits in ACT.

start - [Installation]

rajit (rajit@undisclosed.example.com) — 2026-04-19T13:50:22+00:00

The ACT VLSI Design Tools Welcome to the Wiki for the ACT suite of VLSI design tools. ACT is an Asynchronous Circuit Toolkit which has been built from scratch to support the design and implementation of asynchronous logic. While that is the main goal, the tools we have developed also support synchronous logic as a special case. These tools have been developed primarily by

thank - [Internal Contributors]

rajit (rajit@undisclosed.example.com) — 2026-04-19T13:49:01+00:00

Internal Contributors Members of the asynchronous VLSI and architecture group have been making numerous contributions to the code base. Some have implemented key pieces of the toolflow; others are regular users and have found innumerable bugs and limitations that triggered improvements to the code base and enhancements to functionality. The contributors have been:

fpga - [Usage]

rajit (rajit@undisclosed.example.com) — 2026-04-19T10:54:56+00:00

FPGA modeling ACT is used to describe asynchronous circuits. Mainstream FPGAs from Xilinx, Altera, etc. don't support asynchronous logic synthesis. There have been many point solutions developed by different research groups to map specific asynchronous circuit structures to Xilinx/Altera FPGAs. The mapping approach is usually tailored both to the FPGA tool set and the asynchronous circuit family being mapped.

start - [Implementation and verification]

rajit (rajit@undisclosed.example.com) — 2026-04-18T16:15:45+00:00

Tools In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow.

chp2prs - [Nested Loop Constructs]

rajit (rajit@undisclosed.example.com) — 2026-04-14T19:33:18+00:00

Circuit Synthesis The process of converting a CHP description of a process into a PRS description automatically. Maelstrom Guide work in progress... Maelstrom is a new logic synthesis technique (and software tool) for asynchronous circuits, developed at the AVLSI Lab at Yale. This is a guide to writing CHP so that the tool produces high-quality circuits.

prog_compare.png - created

karthi (karthi@undisclosed.example.com) — 2025-10-14T02:07:27+00:00

customdesign2024.pdf

ben (ben@undisclosed.example.com) — 2024-07-15T16:06:48+00:00

async_lib.pdf

rajit (rajit@undisclosed.example.com) — 2024-07-15T14:39:42+00:00

custom_design.tgz - created

ben (ben@undisclosed.example.com) — 2024-07-15T11:42:36+00:00

asynchronous_design_methodology_using_act_with_commercial_tools.pdf - created

rajit (rajit@undisclosed.example.com) — 2024-07-14T14:38:43+00:00

20_intro.pdf - created

rajit (rajit@undisclosed.example.com) — 2024-07-14T14:38:43+00:00

async_school_2024_-_petri_nets_-_yakovlev_1.0.pdf - created

rajit (rajit@undisclosed.example.com) — 2024-07-12T14:47:19+00:00

petri_nets_primer_-_async_summer_school_2024_-_yakovlev_1.0.pdf - created

rajit (rajit@undisclosed.example.com) — 2024-07-12T14:47:19+00:00

petri_intro.pdf - created

rajit (rajit@undisclosed.example.com) — 2024-07-12T14:47:19+00:00

pipe.tgz - created

rajit (rajit@undisclosed.example.com) — 2024-07-09T10:17:02+00:00

sdt.tgz - created

rajit (rajit@undisclosed.example.com) — 2024-07-09T10:17:02+00:00

gates.tgz - created

rajit (rajit@undisclosed.example.com) — 2024-07-09T10:17:02+00:00