The ACT VLSI design tools

graph - [Datapath logic]

rajit (rajit@undisclosed.example.com) — 2026-06-15T10:58:16+00:00

Timing model and graph To understand how timing analysis for asynchronous circuits works, let's take a very simple example of a ring oscillator. [ inverter ring] if the inverter ring is oscillating, and we make the standard assumption that each signal transition has a fixed delay, then the oscillations of the inverter will have a periodic pattern in time. This basic idea is in fact much more general, and one can show that asynchronous circuits exhibit this sort of periodicity, and it is possi…

start - [Queries]

rajit (rajit@undisclosed.example.com) — 2026-06-14T15:33:25+00:00

Static Timing and Power Analysis ACT includes a static timing and power analysis engine called Cyclone. Cyclone takes an ACT design along with a Liberty file as well as (optional) parasitics to estimate the performance of the circuit, as well as to check any timing constraints required for correct operation.

spec - [Timing directives]

rajit (rajit@undisclosed.example.com) — 2026-06-14T13:41:56+00:00

The spec sublanguage The spec sublanguage is used to specify properties or requirements for the circuit. A standard spec directive has the following syntax: spec { directive_name (sig1, sig2, ...) directive_name (sig1, sig2, ...) ... }

constraints

rajit (rajit@undisclosed.example.com) — 2026-06-14T13:27:08+00:00

Timing constraints Depending on the asynchronous circuit family used, the correct operation of a design may require certain timing constraints to be satisfied. ACT provides a mechanism to specify these timing constraints, and Cyclone can check if the constraints are in fact satisfied using delay information from the timing

start - [Implicit use of the cell library]

rajit (rajit@undisclosed.example.com) — 2026-06-12T18:34:22+00:00

Mapping a design to a cell library For the ASIC flow, each production rule in the design is mapped to a cell. Cells are simply special processes that are used to specify the leaf cells in the layout generation flow. ACT assumes that each cell has associated with it some layout and an associated LEF file. Cells are specified using the same syntax as a process, but using

netlist - [Cell generation and mapping]

rajit (rajit@undisclosed.example.com) — 2026-06-12T16:56:35+00:00

Netlist configuration options The netlist section of the configuration file specifies transistor width defaults, and other information that controls netlist creation from production rules. The configuration file is prs2net.conf, although defaults may be specified in the ACT global configuration.

act2v - [Configuration options]

rajit (rajit@undisclosed.example.com) — 2026-06-11T14:04:26+00:00

ACT netlist to Verilog netlist The act2v tool can be used to convert an ACT structural netlist into Verilog syntax. This is useful if you need a structural Verilog netlist---for example, as an input to a commercial or other third party tool (e.g. for place and route, visualization, etc.).

synth

karthi (karthi@undisclosed.example.com) — 2026-06-10T03:01:08+00:00

Logic Synthesis Configuration This section of the configuration file specifies options for circuit synthesis. It contains some options that are used by all synthesis styles, as well as some that are used by Maelstrom, the latest synthesis style for CHP.

start - [The configuration files]

rajit (rajit@undisclosed.example.com) — 2026-06-07T10:41:57+00:00

ACT Configuration Files There are a number of language features as well as tools that require some combination of technology-independent and technology-dependent information. ACT provides a unified configuration file format that can be used to specify this information. This file is automatically read in when the library is initialized through a call to

start - [Session 2: From Behavior to gates]

rajit (rajit@undisclosed.example.com) — 2026-06-03T14:16:51+00:00

ASYNC 2026 Summer School The 3rd edition of the ASYNC Summer school will be co-located directly before the conference (June 1-2 2026) as a hybrid event at DTU in Lyngby, Denmark. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools.

montek-async2026-mousetrap.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-03T14:16:41+00:00

async-backend.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-03T09:17:40+00:00

async_school_2026_-_petri_nets_-_yakovlev.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-03T06:45:23+00:00

petri_nets_primer_-_async_summer_school_2026_-_yakovlev.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-03T06:45:08+00:00

dataflow-async26-v2.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-02T15:53:49+00:00

10_timing.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-02T12:22:40+00:00

08_nondet.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-01T09:22:28+00:00

07_chp_to_gates.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-01T09:21:14+00:00

04_handshake_protocol.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-01T09:20:06+00:00

05_gates.pdf - created

rajit (rajit@undisclosed.example.com) — 2026-06-01T09:19:36+00:00