https://avlsi.csl.yale.edu/act/ 2026-10-06T02:31:29+00:00 https://avlsi.csl.yale.edu/act/ https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png text/html 2026-10-04T15:30:16+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:actsim&rev=1791127816&do=diff Actsim: an ACT simulator To run actsim, you need to select the ACT file to simulate and the top-level process for your design: % actsim file.act process actsim> A simple example The following ACT file is a CHP example that sends three integers on an output channel, and connects that process to one that simply receives an integer and displays it to the screen. text/html 2026-10-01T10:59:51+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=config:expropt&rev=1790852391&do=diff Expression Synthesis Configuration The synthesis section of the configuration file specifies options for circuit synthesis in general. In particular, it has options for the expression optimizer (expropt), which is the interface between the ACT tool-suite and external logic synthesis tools, such as ABC. We use these external tools to perform synthesis of expressions into combinational logic by emitting Verilog files which correspond to a logical expression, running the synthesis tool to get a m… text/html 2026-09-29T12:43:37+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=config:netlist&rev=1790685817&do=diff Netlist configuration options The netlist section of the configuration file specifies transistor width defaults, and other information that controls netlist creation from production rules. The configuration file is prs2net.conf, although defaults may be specified in the ACT global configuration. text/html 2026-09-26T14:54:30+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=stdoptions:start&rev=1790434470&do=diff Common options Command-line flags ACT tools that use the core act library all accept the following command-line options. These options should come first, before any tool-specific options. Commonly used options The following options tend to be regularly used. text/html 2026-09-26T14:49:47+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=thank&rev=1790434187&do=diff Internal Contributors Members of the asynchronous VLSI and architecture group have been making numerous contributions to the code base. Some have implemented key pieces of the toolflow; others are regular users and have found innumerable bugs and limitations that triggered improvements to the code base and enhancements to functionality. The contributors have been: text/html 2026-09-26T14:45:40+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=start&rev=1790433940&do=diff The ACT VLSI Design Tools Welcome to the Wiki for the ACT suite of VLSI design tools. ACT is an Asynchronous Circuit Toolkit which has been built from scratch to support the design and implementation of asynchronous logic. While that is the main goal, the tools we have developed also support synchronous logic as a special case. These tools have been developed primarily by text/html 2026-09-26T14:42:12+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=install_actflow&rev=1790433732&do=diff Installing actflow Primary development of the tools in the actflow repository is conducted on Linux and MacOS, and so it has been extensively tested on such systems. It has also been tested in certain Windows environments (see below). If you are a Homebrew user, check out the text/html 2026-09-26T13:40:28+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:netgen&rev=1790430028&do=diff prs2net: automated netlist generation The tool prs2net can be used to automatically generate a hierarchical spice netlist from an .act file. Parameters that control defaults and the output format are specified in a configuration file. The overall way the tool works is as follows. First, it reads in the text/html 2026-09-26T12:59:26+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:prs&rev=1790427566&do=diff The prs sublanguage The prs sublanguage is used to specify production rules. Production rules are the syntax used by ACT to specify pull-up and pull-down networks for a gate. For example, an inverter with input a and output b would be specified by the following production rule: text/html 2026-09-26T12:51:29+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:sizing&rev=1790427089&do=diff Sizing sub-language The sizing sub-language is used to simplify gate sizing specifications. The prs sub-language already provides a mechanism to specify sizing, but this can become very verbose. For example, consider an inverter prs { in => out- } text/html 2026-09-25T12:58:45+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:act2dot&rev=1790341125&do=diff Visualize ACT Design It can be helpful to visualize the connectivity between instances in an ACT design. The tool act2dot can be used to visualize the connectivity at the CHP-level of abstraction (default), or the PRS level of abstraction. The usage is similar to text/html 2026-09-25T11:15:39+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:dflow2dot&rev=1790334939&do=diff Visualize Dataflow Graph The dataflow sublanguage allows computations to be specified as dataflow graphs. It can be helpful to visualize these graphs when debugging a design. The dflow2dot tool can be used for this purpose. Its usage is: $ dflow2dot -p top_level file.act text/html 2026-09-25T11:11:56+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:start&rev=1790334716&do=diff Tools In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow. text/html 2026-09-16T21:44:30+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=dockersetup&rev=1789595070&do=diff Docker image and container setup We have provided a Docker image that has all the standard tools we use pre-installed. If you are unfamilar with Docker/containers, there are many online tutorials available (e.g. here). Essentially Docker provides a lightweight text/html 2026-09-13T12:53:49+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=language:expressions&rev=1789304029&do=diff Expressions Expression syntax in ACT is similar to expressions in the C language. * Integer expressions: operators that are supported include +, -, *, /, and % for integer arithmetic operations, and &, |, and ~ for bit-wise logical operations between integers. text/html 2026-09-13T12:09:45+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=config:runtime&rev=1789301385&do=diff ACT Runtime Configuration The behavior of the core ACT library and the way an ACT file is interpreted is typically controlled by command-line options to specific tools. However, there are some common settings that can be selected using a local ACT configuration file and then passed to the ACT tool using the text/html 2026-09-13T12:07:43+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=config:generic&rev=1789301263&do=diff General technology configuration General technology configuration information is stored in global.conf. This file contains information that doesn't depend on most of the details of the technology provided by the foundry. The only item here that could be viewed as technology-specific corresponds to the transistor flavors supported (i.e. different thresholds, I/O transistors, etc). We normally use a fixed set of names for these transistor flavors in the ACT file, independent of technology. text/html 2026-07-13T11:48:51+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?image=summer2026%3Aday2.tar.gz&ns=summer2026&rev=1783943331&tab_details=history&media_do=diff&do=media <img src="https://avlsi.csl.yale.edu/act/lib/images/fileicons/svg/gz.svg" alt="day2.tar.gz" loading="lazy" width="500" height="500" /> text/html 2026-07-13T11:48:11+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?image=summer2026%3Aday1.tar.gz&ns=summer2026&rev=1783943291&tab_details=history&media_do=diff&do=media <img src="https://avlsi.csl.yale.edu/act/lib/images/fileicons/svg/gz.svg" alt="day1.tar.gz" loading="lazy" width="500" height="500" /> text/html 2026-06-25T17:58:13+00:00 rajit (rajit@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?image=summer2026%3A14_customckts.mp4&ns=summer2026&rev=1782410293&tab_details=history&media_do=diff&do=media <img src="https://avlsi.csl.yale.edu/act/lib/images/fileicons/svg/mp4.svg" alt="14_customckts.mp4" loading="lazy" width="500" height="500" />