The ACT VLSI design tools

chp - [Arrays: dynamic v/s non-dynamic indices]

rajit (rajit@undisclosed.example.com) — 2026-07-27T09:45:11+00:00

The chp sublanguage The CHP sublanguage is an evolution of Dijkstra's guarded commands notation and Hoare's CSP. It is a programming notation augmented with send/receive primitives for communication and parallel composition. A chp program is specified in ACT as follows:

runtime - [Decomposition passes]

rajit (rajit@undisclosed.example.com) — 2026-07-26T21:45:55+00:00

ACT Runtime Configuration The behavior of the core ACT library and the way an ACT file is interpreted is typically controlled by command-line options to specific tools. However, there are some common settings that can be selected using a local ACT configuration file and then passed to the ACT tool using the

start - [Command-line flags]

rajit (rajit@undisclosed.example.com) — 2026-07-26T20:36:50+00:00

Common options Command-line flags ACT tools that use the core act library all accept the following command-line options. These options should come first, before any tool-specific options: * -Ttechname: changes the technology configuration files to techname. This specifies that the config files are in directory

start - [From production rules to cells]

rajit (rajit@undisclosed.example.com) — 2026-07-26T12:44:18+00:00

Mapping a design to a cell library For the ASIC flow, each production rule in the design is mapped to a cell. Cells are simply special processes that are used to specify the leaf cells in the layout generation flow. ACT assumes that each cell has associated with it some layout and an associated LEF file. Cells are specified using the same syntax as a process, but using

thank - [External Contributors]

rajit (rajit@undisclosed.example.com) — 2026-07-24T14:19:21+00:00

Internal Contributors Members of the asynchronous VLSI and architecture group have been making numerous contributions to the code base. Some have implemented key pieces of the toolflow; others are regular users and have found innumerable bugs and limitations that triggered improvements to the code base and enhancements to functionality. The contributors have been:

assist

rajit (rajit@undisclosed.example.com) — 2026-07-23T10:50:19+00:00

AI Assistants For those getting started, Ruiqi “Richard” Niu from Johns Hopkins has created skills for LLM agents to write ACT. This was developed during the 2026 Telluride Neuromorphic AI Workshop as part of the work in the RobNIC group (Robotics and Neuromorphic Integrated Circuits).

start - [Asynchronous design]

rajit (rajit@undisclosed.example.com) — 2026-07-23T10:47:51+00:00

The ACT VLSI Design Tools Welcome to the Wiki for the ACT suite of VLSI design tools. ACT is an Asynchronous Circuit Toolkit which has been built from scratch to support the design and implementation of asynchronous logic. While that is the main goal, the tools we have developed also support synchronous logic as a special case. These tools have been developed primarily by

install_actflow - [Linux/Unix-like environments]

rajit (rajit@undisclosed.example.com) — 2026-07-22T15:09:14+00:00

Installing actflow Primary development of the tools in the actflow repository is conducted on Linux and MacOS, and so it has been extensively tested on such systems. It has also been tested in certain Windows environments (see below). If you are a Homebrew user, check out the

expressions - [Expressions]

rajit (rajit@undisclosed.example.com) — 2026-07-21T16:35:52+00:00

Expressions Expression syntax in ACT is similar to expressions in the C language. * Integer expressions: operators that are supported include +, -, *, /, and % for integer arithmetic operations, and &, |, and ~ for bit-wise logical operations between integers.

start - [Session 4: Customizing Circuits]

rajit (rajit@undisclosed.example.com) — 2026-07-13T11:48:53+00:00

ASYNC 2026 Summer School The 3rd edition of the ASYNC Summer school will be co-located directly before the conference (June 1-2 2026) as a hybrid event at DTU in Lyngby, Denmark. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools.

day2.tar.gz - created

rajit (rajit@undisclosed.example.com) — 2026-07-13T11:48:51+00:00

day1.tar.gz - created

rajit (rajit@undisclosed.example.com) — 2026-07-13T11:48:11+00:00

start - [Configuration file]

rajit (rajit@undisclosed.example.com) — 2026-07-10T18:46:32+00:00

xcell: A cell library characterizer xcell is a cell library characterizer. It takes in a configuration file (xcell.conf) and an ACT file that is used to provide the list of cells to be characterized, and runs a large number of SPICE simulations to generate timing and energy tables in the

14_customckts.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:58:13+00:00

13_petrinets.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:53:17+00:00

12_asic2.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:35:18+00:00

11_asic1.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:26:54+00:00

10_timing.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:21:10+00:00

08_nondet.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:19:24+00:00

07_chptogates.mp4 - created

rajit (rajit@undisclosed.example.com) — 2026-06-25T17:19:04+00:00