https://avlsi.csl.yale.edu/act/ 2026-05-11T06:08:47+00:00 https://avlsi.csl.yale.edu/act/ https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png text/html 2026-03-11T14:40:22+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=asic:cells:start&rev=1773240022&do=diff Mapping a design to a cell library For the ASIC flow, each production rule in the design is mapped to a cell. Cells are simply special processes that are used to specify the leaf cells in the layout generation flow. ACT assumes that each cell has associated with it some layout and an associated LEF file. Cells are specified using the same syntax as a process, but using