https://avlsi.csl.yale.edu/act/ 2026-05-10T13:42:38+00:00 https://avlsi.csl.yale.edu/act/ https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png text/html 2024-05-31T18:37:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=asic:timing:cells&rev=1717180676&do=diff Cell library and characterization Cells in the ACT flow are identified via defcell definitions. Typically all the production rules in a design will be mapped to cells that are contained in a cells.act file, as described in the ASIC flow overview. Logic synthesis tools may, in addition, define their own cells for special components that are explicitly instantiated and defined as a text/html 2024-03-21T17:36:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=asic:timing:constraints&rev=1711042596&do=diff Timing constraints Depending on the asynchronous circuit family used, the correct operation of a design may require certain timing constraints to be satisfied. ACT provides a mechanism to specify these timing constraints, and Cyclone can check if the constraints are in fact satisfied using delay information from the timing text/html 2024-09-03T14:06:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=asic:timing:forks&rev=1725372379&do=diff Timing Forks Timing forks are the way timing constraints are specified in the ACT tool flow. Superficially, timing forks resemble a number of different ways timing constraints are specified in other approaches, but there are a number of subtle differences that we detail below. We begin with some of the key theoretical concepts that underpin the use of timing forks in the ACT design flow. text/html 2024-03-29T10:19:11+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=asic:timing:graph&rev=1711707551&do=diff Timing model and graph To understand how timing analysis for asynchronous circuits works, let's take a very simple example of a ring oscillator. [ inverter ring] if the inverter ring is oscillating, and we make the standard assumption that each signal transition has a fixed delay, then the oscillations of the inverter will have a periodic pattern in time. This basic idea is in fact much more general, and one can show that asynchronous circuits exhibit this sort of periodicity, and it is possi… text/html 2024-08-19T12:32:02+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=asic:timing:start&rev=1724070722&do=diff Static Timing and Power Analysis ACT includes a static timing and power analysis engine called Cyclone. Cyclone takes an ACT design along with a Liberty file as well as (optional) parasitics to estimate the performance of the circuit, as well as to check any timing constraints required for correct operation.