The ACT VLSI design tools - intro_example

alu

Anonymous (anonymous@undisclosed.example.com) — 2025-04-21T23:49:04+00:00

ALU Let's say we want to design an ALU that takes two data inputs, and one control input. The output should be the sum of the two data inputs if the control is zero, the difference if the control is one, the logical AND if the control is two, and the logical OR if the control is three.

assertions

Anonymous (anonymous@undisclosed.example.com) — 2025-05-17T12:07:44+00:00

Assertions Sometimes parameterized components are only valid for certain parameter ranges. ACT includes assertions that are checked at expansion time that can be used to validate the assumptions made. As a simple example, suppose we want to define an N-place buffer.

basicprs

Anonymous (anonymous@undisclosed.example.com) — 2022-05-30T14:16:15+00:00

Basic gate-level simulation Gates in the ACT language are specified using production rules, which can specify the Boolean logic for the pull-up and pull-down switching networks for a gate. Since production rules are general enough to specify arbitrary pull-up and pull-down networks, ACT can be used to describe both synchronous and asynchronous circuits. The ACT language contains many constructs that can be used to create design hierarchy, simplifying the description of the circuit. Components …

cadence_import

Anonymous (anonymous@undisclosed.example.com) — 2024-03-13T13:50:30+00:00

Introduction This guide is intended to explain how to export asynchronous circuits designed in ACT and import them in Cadence Virtuoso to simulate their functioning. Some steps are needed to get the Verilog netlist and some editing to let the netlist be valid and more readable. These steps are shown referring to one of the most basic circuits starting from its behavioral description.

chp_fifo

Anonymous (anonymous@undisclosed.example.com) — 2025-05-01T15:36:11+00:00

First-in first-out buffer in CHP (It is a bit unfortunate that the computer science community uses the term buffer to refer to a fifo, while the circuits community uses the term buffer to refer to an electrical circuit that introduces gain to improve signal drive strength.)

chp_fifo2

Anonymous (anonymous@undisclosed.example.com) — 2025-05-01T10:47:50+00:00

Alternate Buffer We start with the earlier example of a templated buffer: template defproc buffer (chan?(int) L; chan!(int) R) { one_place_buffer b[N]; (i : N-1 : b[i].R = b[i+1].L;) b[0].L = L; b[N-1].R = R; } In this version, we used the

connection_info

Anonymous (anonymous@undisclosed.example.com) — 2025-05-18T15:02:37+00:00

Connections There are two categories of variables in ACT: parameter variables (e.g. pint, pbool, etc.) that are used during expansion/elaboration time to build a circuit, and circuit component/wire variables. While parameter variables are more like normal variables in a programming language with the caveat that in some contexts they are

dependencies

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:20+00:00

Dependencies Any complex design will involve a large number of ACT files and namespaces. For a hierarchical design with many imported libraries, it is useful to be able to determine dependency information and see if all the libraries are present in the directories where ACT can find them. The command

files

Anonymous (anonymous@undisclosed.example.com) — 2025-05-22T10:10:10+00:00

Organizing files in a project There are different ways to organize the files in a complex design project. Normally one has a number of different .act files that are combined using import directives to form the design. When an import directive is encountered, the ACT tools search for the

gates

Anonymous (anonymous@undisclosed.example.com) — 2022-05-13T13:18:50+00:00

Simple combinational gates The following specifies a number of combinational gates, where the process names correspond to the commonly used names for the gates. defproc inverter (bool? i; bool! o) { prs { i => o- } } defproc nand2 (bool? a, b; bool! c) { prs { a & b => c- } } defproc nor2 (bool? a, b; bool! c) { prs { a | b => c- } }

inverter

Anonymous (anonymous@undisclosed.example.com) — 2025-05-01T13:32:49+00:00

A simple inverter ACT is used to describe a hierarchical collection of processes that together implement a circuit. Each process is an independent entity, and operates concurrently with all the other processes in the system. Circuits are also processes, and the physical implementation of two circuits operate concurrently.

loops

Anonymous (anonymous@undisclosed.example.com) — 2025-08-24T16:48:16+00:00

Array, loops and selection Complex datapath designs are often designed with array of simpler cells. The following example show how to create array of simple cells and connect them using loop constructs in ACT. import "adder.act"; defproc adder8b ( bool? a[8],b[8],ci; bool! s[8],co) { bool c[9]; fulladder fa[8]; c[0] = ci; co = c[8]; ( i : 8 : fa[i](a[i], b[i], c[i], s[i], c[i+1]);) }

namespace

Anonymous (anonymous@undisclosed.example.com) — 2025-05-17T11:51:45+00:00

Creating a library of building blocks A library can be created using pre-designed building blocks and use them in hierarchical designs. This can be achieved using keyword import. In this case, ACT file begins with a sequence of “import” statements. The

name_mangling

Anonymous (anonymous@undisclosed.example.com) — 2025-05-20T12:18:45+00:00

Expanded names and name mangling Two useful concepts to keep in mind when using the ACT tools are expanded names and mangled names. Expanded names Expanded names are the names generated internally by ACT when expanding a design (or elaborating a design). This is a concept one should be familiar with, especially when debugging and/or understanding error messages. This is best illustrated with an example. Consider the following templated process definition:

netlist

Anonymous (anonymous@undisclosed.example.com) — 2022-05-13T13:22:10+00:00

Generating spice netlist and simulation with Xyce Files required: * [Simple BSIM3 model file] from a (very old) MOSIS SCMOS_SUBM 0.6um run, from a time when everything was publicly posted. Save this to model.sp. (1) Input file with gate sizing The following inv.act file will be used as a test case for SPICE simulation.

operators

Anonymous (anonymous@undisclosed.example.com) — 2025-05-07T18:34:05+00:00

Operators A special case of pure structures are those that are used to hold arithmetic types. For example, an example pure structure corresponding to a sign-magnitude integer is: template deftype signed_int(bool neg; int val) { } It is convenient to be able to define arithmetic on

pure_struct

Anonymous (anonymous@undisclosed.example.com) — 2025-05-18T15:07:31+00:00

Using pure structures A pure structure is a user-defined data type that contains only int/bool or other pure structures. Pure structures are analogous to C/C++ structs, and can be used to organize data and make CHP more human-readable. An example of a pure structure is:

sizing

Anonymous (anonymous@undisclosed.example.com) — 2022-05-13T13:21:46+00:00

Specifying gate sizes The gate sizing can be specified using prs sub-language but using the newly introduced sizing sub-language is recommended. This tutorial will show how to specify gate sizes using the new sizing sub-language. Before writing a prs for inverter, let’s assume that we have the following specification included in the configuration file. Here,

standard_sim

Anonymous (anonymous@undisclosed.example.com) — 2025-05-14T18:40:51+00:00

Using standard environments Simulating CHP programs often requires creating an environment to inject data into the circuit being tested, and an environment that reads the outputs of the circuit to check their values. actsim comes with a simulation library that has some common functionality that can be used for this purpose.

start

Anonymous (anonymous@undisclosed.example.com) — 2025-08-24T16:46:37+00:00

ACT By Example ACT is a hardware description language that has been influenced more by programming languages developed for software rather than hardware. The key difference between ACT and normal software programming languages is that when “variables

templates

Anonymous (anonymous@undisclosed.example.com) — 2022-05-13T13:21:16+00:00

Parameterized design using templates Template provides a good way to create a parameterized design framework which can be used to get customized design from a generic design based on user input. ACT supports templates to create parameterized types, channel, and processes.

template_deps

Anonymous (anonymous@undisclosed.example.com) — 2025-05-07T18:26:20+00:00

Dependent templates We've already seen how template parameters can be used to construct parameterized circuits, as well as change the size of arrays in the process port list. In addition, they can also be used to specify parameters used in the template itself. template defproc test(chan!(int) out) { chp { (; i : N : out!data[i]) } }