The ACT VLSI design tools - language:langs
https://avlsi.csl.yale.edu/act/
2026-05-11T15:11:56+00:00The ACT VLSI design tools
https://avlsi.csl.yale.edu/act/
https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.pngtext/html2025-11-17T18:26:28+00:00Anonymous (anonymous@undisclosed.example.com)chp
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:chp&rev=1763403988&do=diff
The chp sublanguage
The CHP sublanguage is an evolution of Dijkstra's guarded commands notation and Hoare's CSP. It is a programming notation augmented with send/receive primitives for communication and parallel composition. A chp program is specified in ACT as follows:text/html2024-07-22T17:54:05+00:00Anonymous (anonymous@undisclosed.example.com)dflow
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:dflow&rev=1721670845&do=diff
The dataflow sublanguage
The dataflow sublanguage provides a convenient short-hand when designing asynchronous circuits using pipelined asynchronous circuits. The dataflow language operates exclusively on channels, and treats channels as variables to specify the dataflow computation.text/html2022-05-13T12:50:43+00:00Anonymous (anonymous@undisclosed.example.com)hse
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:hse&rev=1652446243&do=diff
The hse sublanguage
The handshaking expansion language uses the same syntax as CHP, with the following restrictions:
* All variables are Boolean-valued
* Communication actions are not permitted; they should be expanded into handshake protocols, hence the nametext/html2024-08-07T11:09:51+00:00Anonymous (anonymous@undisclosed.example.com)prs
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:prs&rev=1723028991&do=diff
The prs sublanguage
The prs sublanguage is used to specify production rules. Production rules are the syntax used by ACT to specify pull-up and pull-down networks for a gate. For example, an inverter with input a and output b would be specified by the following production rule:text/html2025-07-21T19:47:30+00:00Anonymous (anonymous@undisclosed.example.com)refine
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:refine&rev=1753127250&do=diff
The refine sublanguage
The refine sub-language takes the form
refine {
/* any standard ACT body element can appear here */
}
This is used to provide an implementation of a process that replaces the CHP, dataflow, HSE, or PRS body. For example, imagine you had a process defined at the CHP leveltext/html2025-08-31T16:04:08+00:00Anonymous (anonymous@undisclosed.example.com)sizing
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:sizing&rev=1756656248&do=diff
Sizing sub-language
The sizing sub-language is used to simplify gate sizing specifications. The prs sub-language already provides a mechanism to specify sizing, but this can become very verbose. For example, consider an inverter
prs {
in => out-
}text/html2024-12-19T12:18:38+00:00Anonymous (anonymous@undisclosed.example.com)spec
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:spec&rev=1734610718&do=diff
The spec sublanguage
The spec sublanguage is used to specify properties or requirements for the circuit. A standard spec directive has the following syntax:
spec {
directive_name (sig1, sig2, ...)
directive_name (sig1, sig2, ...)
...
}text/html2022-07-11T11:43:49+00:00Anonymous (anonymous@undisclosed.example.com)start
https://avlsi.csl.yale.edu/act/doku.php?id=language:langs:start&rev=1657539829&do=diff
Hardware description and specification languages
ACT permits the specification and description of circuits at multiple levels of abstraction. These languages are embedded into ACT as sub-languages. These sub-languages can be used to specify circuits in a variety of ways and at different levels of abstraction. Some sub-languages are only useful when combined with others.