The ACT VLSI design tools - scratch

configtut

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Configuration file So far we have learned how to describe a circuit in ACT, simulate using prsim and irsim. Now, we will move on to the next stage i.e. designing CMOS circuits from ACT description. The process of designing circuit often starts with creating a spice netlist to simulate transistor-level circuit behavior. In order to generate a spice netlist, ACT requires some technology-dependent information and information to understand designer’s intent. We use configuration files to provide su…

loops

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Array, loops and selection Complex datapath designs are often designed with array of simpler cells. The following example show how to create array of simple cells and connect them using loop constructs in ACT. import "adder.act"; defproc adder8b ( bool? a[8],b[8],ci; bool! s[8],co) { bool c[9]; fulladder fa[8]; c[0] = ci; co = c[8]; ( i : 8 : fa[i](a[i], b[i], c[i], s[i], c[i+1]);) }

namespace

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Creating a library of building blocks A library can be created using pre-designed building blocks and use them in hierarchical designs. This can be achieved using keyword import. In this case, ACT file begins with a sequence of “import” statements. The

netlist

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Generating spice netlist and simulation with Xyce Files required: * inv.act * inv.sp * test_inv.sp * on_c5n.sp (1) Input file with gate sizing defproc inv (bool? i; bool! o) { prs { i => o- } } template defproc szinv <: inv() { sizing { o {-drive} } } defproc INVX1 <: szinv<1> () { } defproc INVX2 <: szinv<2> () { } INVX1 A1; INVX2 A2;

sizing

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Specifying gate sizes The gate sizing can be specified using prs sub-language but using the newly introduced sizing sub-language is recommended. This tutorial will show how to specify gate sizes using the new sizing sub-language. Before writing a prs for inverter, let’s assume that we have the following specification included in the configuration file. Here,

start

Anonymous (anonymous@undisclosed.example.com) — 2025-08-01T13:54:20+00:00

Scratch space Put pages in this namespace while drafting items. Basic circuits * tutorial 1 - A simple inverter covering (production rules, prs block, defproc incl. in/out, instantiation, aflat and prsim) * tutorial 2 - More combinational gates * Creating libraries and namespaces * Best practices for organizing a complex project * Array,

templates

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Parameterized design using templates Template provides a good way to create a parameterized design framework which can be used to get customized design from a generic design based on user input. ACT supports templates to create parameterized types, channel, and processes.

tutorial_1_-_a_simple_inverter

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

A simple inverter In this first example we will build and simulate an inverter and touch the basic language elements and tools needed for this (production rules, prs block, defproc incl. in/out, instantiation, aflat and prsim) make sure you installed act and added it to your path please follow

tutorial_2_-_more_combinational_gates

Anonymous (anonymous@undisclosed.example.com) — 2020-12-02T06:00:22+00:00

Simple combinational gates In this tutorial we will go a step further and look at multiple inputs, local variables and how to connect cells, as well as a more complex simulator. The following specifies a number of combinational gates, where the process names correspond to the commonly used names for the gates.