<?xml version="1.0" encoding="UTF-8"?>
<!-- generator="FeedCreator 1.8" -->
<?xml-stylesheet href="https://avlsi.csl.yale.edu/act/lib/exe/css.php?s=feed" type="text/css"?>
<rdf:RDF
    xmlns="http://purl.org/rss/1.0/"
    xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
    xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
    xmlns:dc="http://purl.org/dc/elements/1.1/">
    <channel rdf:about="https://avlsi.csl.yale.edu/act/feed.php">
        <title>The ACT VLSI design tools - sim</title>
        <description></description>
        <link>https://avlsi.csl.yale.edu/act/</link>
        <image rdf:resource="https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png" />
       <dc:date>2026-04-14T21:45:36+00:00</dc:date>
        <items>
            <rdf:Seq>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:file&amp;rev=1709054205&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:inf_buffer&amp;rev=1708987675&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:loggers&amp;rev=1708982124&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:rng&amp;rev=1708716405&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:scoreboards&amp;rev=1712669595&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:sinks&amp;rev=1708962578&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:sources&amp;rev=1708712353&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:splitter&amp;rev=1709055540&amp;do=diff"/>
                <rdf:li rdf:resource="https://avlsi.csl.yale.edu/act/doku.php?id=sim:start&amp;rev=1709048619&amp;do=diff"/>
            </rdf:Seq>
        </items>
    </channel>
    <image rdf:about="https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png">
        <title>The ACT VLSI design tools</title>
        <link>https://avlsi.csl.yale.edu/act/</link>
        <url>https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png</url>
    </image>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:file&amp;rev=1709054205&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-27T17:16:45+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>file</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:file&amp;rev=1709054205&amp;do=diff</link>
        <description>File interaction

This library exports functions for basic file interaction. The exposed functions enable you to read integer data from a basic input file, and to dump integer values into an output file. While this is rather basic, the file API can be extended using a shared C++ library and an actsim configuration file.</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:inf_buffer&amp;rev=1708987675&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-26T22:47:55+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>inf_buffer</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:inf_buffer&amp;rev=1708987675&amp;do=diff</link>
        <description>Infinite capacity buffer

If you need to prevent components from a token producing part of the design from influencing a token consuming part of the design (for example token sequencers and design under test from a scoreboard in a testing harness), you need a way to decouple these two partitions. The best way to do so is an infinite capacity buffer. This simulation library offers such a construction; however it is obviously not synthesizable.</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:loggers&amp;rev=1708982124&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-26T21:15:24+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>loggers</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:loggers&amp;rev=1708982124&amp;do=diff</link>
        <description>Loggers

If you need to regularly check what kind of data is flowing over a certain channel, you can use loggers to more elegantly watch the activity. A logger will only report tokens of data values successfully transmitted over the channel and thus hopefully help unclog your log and ease your debugging experience. We offer two different loggers, one logging to console and one logging to a file.</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:rng&amp;rev=1708716405&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-23T19:26:45+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>rng</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:rng&amp;rev=1708716405&amp;do=diff</link>
        <description>Randomness

The sim::rand namespace contains support for random number generation, and includes the definition of a number of processes that use this random number generation functionality. The underlying random number generator used is a pseudo-random number generator, and hence the sequence of</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:scoreboards&amp;rev=1712669595&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-04-09T13:33:15+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>scoreboards</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:scoreboards&amp;rev=1712669595&amp;do=diff</link>
        <description>Scoreboards

When validating a hardware design, it is important to run a large number of tests through a design. Commonly, the results of these tests are either compared against a known good output or, for more involved designs, matched with the outputs of a (often not synthesizable) model performing the same operations.</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:sinks&amp;rev=1708962578&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-26T15:49:38+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>sinks</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:sinks&amp;rev=1708962578&amp;do=diff</link>
        <description>Sinks

Sinks are the opposite of sources. They simply consume tokens from a channel. While sinks may sound like they would be on the other end of a verification setup to sources, this library actually provides another type of sink: A  scoreboard. This type of sink compares the values it receives to a reference value. When verifying a design, this type of sink should be used instead. To keep this group separate, this library only provides two types of (single-ended) simple sink.</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:sources&amp;rev=1708712353&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-23T18:19:13+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>sources</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:sources&amp;rev=1708712353&amp;do=diff</link>
        <description>Sources

For all data origin types, there are four sources providing it. This is by design: Ever source has a version with a single output channel and one with a configurable number of output channels (names contain _multi). On top of that, each of those versions has a variation which will always be enabled, and one which has an enable flag exposed (names contain</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:splitter&amp;rev=1709055540&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-27T17:39:00+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>splitter</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:splitter&amp;rev=1709055540&amp;do=diff</link>
        <description>Splitter

If you need to replicate tokens from a single channel to multiple channels, you can use this splitter. While the function of this process is rather generic, this specific implementation is meant for the simulation library and should not be used for final designs. It contains logging functionality meant for testing and verification.</description>
    </item>
    <item rdf:about="https://avlsi.csl.yale.edu/act/doku.php?id=sim:start&amp;rev=1709048619&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-02-27T15:43:39+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>start</title>
        <link>https://avlsi.csl.yale.edu/act/doku.php?id=sim:start&amp;rev=1709048619&amp;do=diff</link>
        <description>Simulation library

The simulation library is a collection of components which will aid you in testing and verifying your designs. Components in this library are decidedly not synthesizable and should never be included in a final design. A lot of the components use actsim&#039;s capability to call external C functions from within CHP code.</description>
    </item>
</rdf:RDF>
