https://avlsi.csl.yale.edu/act/ 2026-05-10T09:49:45+00:00 https://avlsi.csl.yale.edu/act/ https://avlsi.csl.yale.edu/act/lib/exe/fetch.php?media=wiki:logo.png text/html 2026-03-11T14:39:25+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:act2lef&rev=1773239965&do=diff Converting an ACT design into LEF/DEF act2lef can convert an ACT file into a LEF/DEF suitable for a place and route flow. This tool is now deprecated, and its functionality is replaced by the much more flexible interact tool. Please see the physical implementation documentation for details on generating LEF and DEF. text/html 2026-03-11T14:36:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:act2v&rev=1773239817&do=diff ACT netlist to Verilog netlist The act2v tool can be used to convert an ACT structural netlist into Verilog syntax. This is useful if you need a structural Verilog netlist---for example, as an input to a commercial or other third party tool (e.g. for place and route, visualization, etc.). text/html 2026-05-03T17:00:48+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:actsim&rev=1777827648&do=diff Actsim: an ACT simulator To run actsim, you need to select the ACT file to simulate and the top-level process for your design: % actsim file.act process actsim> A simple example The following ACT file is a CHP example that sends three integers on an output channel, and connects that process to one that simply receives an integer and displays it to the screen. text/html 2024-07-27T10:04:11+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:adepend&rev=1722074651&do=diff adepend This is modeled on the makedepend tool used for C/C++ programs that can be used to automatically produce file dependencies for make files. Given an ACT file, adepend will produce a one-line output that shows the dependency of the ACT file on others. text/html 2025-10-08T14:51:59+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:basebnf&rev=1759935119&do=diff Built-in BNF items for pgen The built-in BNF items for ''pgen'' are: * INT: integers * REAL: real numbers * ID: C-style identifiers * STRING: strings * expr: C-style expressions of any type * int_expr: integer expressions * bool_expr: Boolean expressions text/html 2025-10-08T14:53:03+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:bnfsyntax&rev=1759935183&do=diff BNF Short Cuts The complete list of short-cuts for specifying a BNF are: * [ things to parse go here ] : an optional list of things to parse. * { things to parse go here “keyword” }** : a keyword separated list of things to parse. * { one-thing text/html 2026-04-14T19:33:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:chp2prs&rev=1776195198&do=diff Circuit Synthesis The process of converting a CHP description of a process into a PRS description automatically. Maelstrom Guide work in progress... Maelstrom is a new logic synthesis technique (and software tool) for asynchronous circuits, developed at the AVLSI Lab at Yale. This is a guide to writing CHP so that the tool produces high-quality circuits. text/html 2020-12-02T06:00:22+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:ext2sp&rev=1606888822&do=diff ext2sp ext2sp converts a (hierarchical) magic extract file into a hierarchical spice file for simulation with SPICE simulators like Xyce or ngspice. Running the tool is straightforward: ext2sp file.ext > file.spice will convert the hierarchical extract file into the corresponding spice file. For this to work properly, there are a number of configuration parameters that are set in the ACT configuration file. text/html 2026-04-19T10:54:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:fpga&rev=1776596096&do=diff FPGA modeling ACT is used to describe asynchronous circuits. Mainstream FPGAs from Xilinx, Altera, etc. don't support asynchronous logic synthesis. There have been many point solutions developed by different research groups to map specific asynchronous circuit structures to Xilinx/Altera FPGAs. The mapping approach is usually tailored both to the FPGA tool set and the asynchronous circuit family being mapped. text/html 2026-05-07T17:33:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:netgen&rev=1778175220&do=diff prs2net: automated netlist generation The tool prs2net can be used to automatically generate a hierarchical spice netlist from an .act file. Parameters that control defaults and the output format are specified in a configuration file. The overall way the tool works is as follows. First, it reads in the text/html 2025-10-08T14:51:09+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:pgen&rev=1759935069&do=diff Parser Generator The parser generator program pgen can be used to quickly develop a parser. It has quite a few built-in features (which may or may not be a good thing depending on what you're trying to do). Based on an input file, the program will create: text/html 2026-03-11T14:41:47+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:prs2cells&rev=1773240107&do=diff ACT cell mapper prs2cells maps production rules into a cell library. This tool is now deprecated, as it is subsumed by the interact tool. Please see the documentation on mapping a design to a cell library. text/html 2020-12-02T06:00:22+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:prs2sim&rev=1606888822&do=diff prs2sim A hierarchical ACT file can be converted into a .sim and .al file for simulation with other open-source tools like irsim or cosmos. Since .sim files correspond to a CMOS netlist, your production rules must be directly CMOS-implementable. This means that any pull-up network must have only inverted variables, and pull-down networks must have only uninverted variables. An explanation of how the production rules are translated into a transistor-level implementation can be found in the text/html 2025-05-01T13:27:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:prsim&rev=1746106039&do=diff prsim: Production rule simulation Note: prsim is now deprecated; please use actsim instead. Before using prsim to simulate a set of production rules, they must first be flattened using aflat. Assuming your production rules are in a file called circuit.act text/html 2026-04-18T16:15:45+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:start&rev=1776528945&do=diff Tools In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow. text/html 2025-07-25T16:22:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://avlsi.csl.yale.edu/act/doku.php?id=tools:v2act&rev=1753460526&do=diff Verilog netlist to ACT The v2act tool can be used to translate a Verilog netlist into ACT format. This program is used internally by the ACT expression optimization library to invoke third-party logic synthesis tools and incorporate their output back into an ACT design. It has been tested against Verilog netlists generated by Synopsys design compiler, Cadence's Genus, yosys, and abc.