_HiStOrY_V2_
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
status\040U\012
watch\040m.l.r\012
step\040100\012
quit\012
step\04010\012
quit\012
cycle\012
quit\012
cycle\012
status\040U\012
quit\012
status\040U\012
quit\012
step\040100\012
status\040U\012
get\040b.m[2].ctrl\012
fanin\040b.m[2].ctrl\012
fanout\040b.m[2].ctrl\012
get\040b.m[2].Reset\012
get\040b.m[2].l.r\012
get\040b.m[2].l.a\012
get\040b.m[2].r.r\012
get\040b.m[2].r.a\012
get\040b.m[2].r.a\012
quit\012
source\040test.scr\012
step\040100\012
quit\012
source\040test.scr\012
get\040b.m[0].bx\012
get\040b.m[0].bx._Y\012
fanout\040b.m[0].bx._Y\012
get\040b.m[0].bx.Y\012
get\040b.m[0].bx.B\012
\012
get\040b.m[0].bx.A\012
get\040b.m[0].l.r\012
quit\012
get\040b.m[0].r.r\012
get\040b.m[0].l.r\012
quit\012
quit\012
get\040b.m[0].r.r\012
get\040b.m[1].r.r\012
get\040b.m[2].r.r\012
get\040b.m[0].r.a\012
get\040b.m[1].r.a\012
get\040b.m[2].r.a\012
quit\012
status\040U\012
step\04010\012
quit\012
set\040Reset\0401\012
set\040b.m[0].l.r\0400\012
cycle\012
status\040U\012
quit\012
cycle\012
quit\012
status\040U\012
step\04010\012
ste0\04010\012
step\040100\012
quit\012
status\040U\012
set\040t.b.l.d[0]\0400\012
set\040b.l.d[0]\0400\012
set\040b.l.d[1]\0400\012
set\040b.l.d[2]\0400\012
set\040b.l.d[3]\0400\012
set\040b.l.d[4]\0400\012
cycle\012
status\040U\012
set\040t.b.m[0].bx\012
get\040b.m[0].bx\012
get\040b.m[0].bx._Y\012
get\040b.m[0].bx.A\012
get\040b.l.r\012
set\040b.l.r\0400\012
set\040b.r.a\0400\012
cycle\012
status\040U\012
watch\040b.r.dpath[4]\012
watch\040b.r.d[4]\012
set\040b.l.d[4]\0401\012
cycle\012
set\040b.l.r\0401\012
cycle\012
quit\012
source\040res.scr\012
status\040U\012
cycle\012
status\040U\012
set\040b.l.r\0401\012
cycle\012
set\040b.l.r\0400\012
cycle\012
set\040b.r.a\0401\012
cycle\012
set\040b.r.a\0400\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
step\040100\012
quit\012
source\040res.scr\012
status\040U\012
cycle\012
status\040U\012
\012
set\040b.l.d[0]\0401\012
cycle\012
set\040b.l.r\0401\012
cycle\012
set\040b.l.d[0]\0401\012
set\040b.l.d[0]\0400\012
cycle\012
set\040b.l.r\0400\012
cycle\012
set\040b.r.a\0401\012
cycle\012
quit\012
set\040b.r.a\0400\012
cycle\012
status\040U\012
get\040b.l.d[7]\012
get\040b.l.d[6]\012
get\040b.l.d[5]\012
get\040b.l.d[4]\012
get\040b.l.d[3]\012
get\040Reset\012
get\040b.l.d[2]\012
get\040b.l.d[1]\012
quit\012
source\040x.scr\012
status\040U\012
quit\012
quit\012
get\040b.l.r\012
fanin\040b.l.r\012
get\040b.l.r\012
get\040b.l.r\012
quit\012
cycle\012
quit\012
status\040U\012
\012
set\040b.l.r\0400\012
set\040b.r.a\0400\012
cycle\012
status\040U\012
set\040b.l.d[0]\0400\012
set\040b.l.d[1]\0400\012
set\040b.l.d[2]\0400\012
set\040b.l.d[3]\0400\012
set\040b.l.d[4]\0400\012
set\040b.l.d[5]\0400\012
set\040b.l.d[6]\0400\012
set\040b.l.d[7]\0400\012
cycle\012
status\040U\012
set\040b.l.r\0401\012
watch\040b.r.r\012
watch\040b.l.a\012
cycle\012
get\040b.r.r\012
set\040b.l.r\0400\012
cycle\012
set\040b.r.a\0401\012
cycle\012
quit\012
status\040U\012
get\040b.r.a\012
set\040b.r.a\0400\012
cycle\012
quit\012
status\040U\012
step\040\012
set\040b.r.a\0400\012
status\040U\012
step\012
step\012
step\012
step\012
watch\040m.b[0].dpath[0]._q\012
watch\040b.m[0].dpath[0]._q\012
quit\012
set\040b.r.a\0400\012
watch\040b.l.r\012
watch\040b.l.d[0]\012
watch\040b.l.d[1\012
watch\040b.l.d[1]\012
cycle\012
quit\012
cycle\012
status\040U\012
get\040b.r.r\012
get\040b.r.d[0]\012
get\040b.r.d[1]\012
get\040b.r.d[2]\012
get\040b.r.d[3]\012
set\040b.r.a\0401\012
cycle\012
get\040b.r.r\012
get\040b.r.d[0]\012
get\040b.r.d[1]\012
get\040b.r.d[2]\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
step\040100\012
quit\012
status\040U\012
quit\012
status\040U\012
step\04010\012
quit\012
step\040100\012
step\040100\012
step\040100\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
step\0401000\012
quit\012
\012
watch\040b.l.r\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
qiut\012
cycle\012
quit\012
cycle\012
quit\012
status\040u\012
stsatus\040U\012
status\040X\012
quit\012
source\040x.src\012
cycle\012
quit\012
source\040x.src\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
source\040x.src\012
cycle\012
l.aquit\012
quit\012
cycle\012
quit\012
source\040x.src\012
cycle\012
quit\012
cycle\012
quit\012
source\040x.src\012
cycle\012
quit\012
source\040x.scr\012
source\040x.src\012
cycle\012
quit\012
source\040x.src\012
cycle\012
quit\012
source\040x.src\012
cycle\012
quit\012
source\040x.src\012
step\040100\012
quit\012
source\040x.src\012
step\04010\012
step\04010\012
quit\012
source\040x.src\012
step\04020\012
quit\012
source\040x.src\012
step\040100\012
qiut\012
quit\012
source\040x.src\012
step\04020\012
quit\012
quit\012
source\040x.src\012
step\040100\012
step\040100\012
\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
cycle\012
quit\012
cycle\012
\012
\012
\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
source\040x.src\012
cycle\012
quit\012
source\040x.src\012
step\040100\012
quit\012
step\040100\012
quit\012
step\040100\012
quit\012
cycle\012
quit\012
step\040100\012
quit\012
step\040100\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
random\012
cycle\012
\012
quit\012
cycle\012
\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
