_HiStOrY_V2_
status\040U\012
set\040l.r\0400\012
set\040r.a\0400\012
cycle\012
status\040U\012
quit\012
set\040Reset\0401\012
cycle\012
status\040U\012
get\040l.a\012
quit\012
set\040Reset\0401\012
cycle\012
status\040U\012
get\040l.a\012
set\040r.r\012
get\040l.r\012
status\040U\012
set\040Reset\0400\012
cycle\012
watch\040l.r\040l.a\040l.d[0]\012
watch\040r.r\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
set\040r.a\0401\012
cycle\012
set\040l.d[0]\0401\012
cycle\012
set\040l.r\0401\012
cycle\012
get\040l.a\012
get\040r.a\012
set\040r.a\0400\012
cycle\012
watch\040r.d[0]\012
get\040r.d[0]\012
set\040l.r\0400\012
cycle\012
quit\012
status\040U\012
set\040Reset\0401\012
cycle\012
status\040U\012
quit\012
set\040Reset\0401\012
get\040l.d[0]\012
get\040f.l.d[0]\012
get\040f.r.d[0]\012
quit\012
status\040U\012
watch\040f.r.d[0]\012
watch\040f.l.d[0]\012
set\040f.l.r\0401\012
get\040f.l.r\012
cycle\012
get\040f.l.a\012
quit\012
status\040U\012
get\040Reset\012
cycle\012
get\040Reset\012
set\040f.l.r\0401\012
watch\040f.l.d[0]\012
watch\040f.r.d[0]\012
watch\040f.r.r\012
cycle\012
get\040f.r.a\012
set\040f.l.r\0400\012
cycle\012
get\040f.r.a\012
set\040f.l.d[0]\0401\012
set\040f.l.r\0401\012
cycle\012
quit\012
cycle\012
status\040U\012
set\040f.l.r\0401\012
cycle\012
set\040f.l.r\0400\012
cycle\012
quit\012
cycle\012
set\040f.l.r\0401\012
cycle\012
status\040U\012
quit\012
cycle\012
set\040f.l.r\0401\012
cycle\012
set\040f.l.r\0400\012
cycle\012
set\040f.l.r\0401\012
cycle\012
set\040f.l.r\0400\012
cycle\012
get\040f.r.a\012
get\040f.r.r\012
status\040U\012
status\0400\012
status\0401\012
watch\040f.r.d[0]\012
watch\040f.r.r\012
set\040f.l.d[0]\0401\012
set\040f.l.r\0401\012
cycle\012
quit\012
cycle\012
status\040U\012
step\012
quit\012
cycle\012
quit\012
!vi\012
quit\012
quit\012
cycle\012
quit\012
cycle\012
quit\012
quit\012
get\040Reset\012
status\040U\012
set\040r.d[0]\0400\012
set\040f[0].r.d[0]\0400\012
step\012
set\040f[1].r.d[0]\0400\012
step\04010\012
step\040100\012
step\040100\012
step\040100\012
step\040100\012
get\040f[0].l.r\012
quit\012
get\040f[0].l.r\012
set\040f[0].l.r\0400\012
step\040100\012
status\040U\012
cycle\012
get\040Reset\012
get\040l.r\012
set\040l.r\0401\012
cycle\012
status\040U\012
quit\012
source\040x.scr\012
status\040U\012
set\040l.r\0401\012
step\040100\012
get\040l.d[0]\012
quit\012
source\040x.scr\012
status\040U\012
set\040l.r\0401\012
cycle\012
get\040f[0].r.d[0]\012
get\040f[1].r.d[0]\012
quit\012
source\040x.scr\012
get\040l.d[0]\012
cycl\012
cycle\012
set\040l.r\0401\012
step\040100\012
quit\012
source\040x.scr\012
cycle\012
status\040U\012
quit\012
cycle\012
quit\012
!vi\012
quit\012
source\040x.scr\012
status\040U\012
get\040Reset\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
set\040l.d[0]\0401\012
cycle\012
set\040l.r\0401\012
cycle\012
quit\012
source\040x.scr\012
status\040U\012
set\040l.d[0]\0401\012
cycle\012
set\040l.r\0401\012
cycle\012
quit\012
source\040x.scr\012
cycle\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
set\040l.d[0]\0401\012
cycle\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
quit\012
source\040x.scr\012
status\040U\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
set\040l.d[0]\0401\012
cycle\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
quit\012
source\040x.scr\012
set\040l.r\0401\012
cycle\012
set\040l.r\0400\012
cycle\012
set\040l.d[0]\0401\012
cycle\012
set\040l.r\0401\012
cycle\012
quit\012
