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Robert Karmazin, Carlos Tadeo Ortega Otero, and Rajit Manohar
Asynchronous circuits are an attractive option to
overcome many challenges currently faced by chip designers,
such as increased process variation. However, the lack of CAD
tools to generate asynchronous circuits limits the adoption of this
promising technology. In this absence of CAD tools, the most
time consuming part of chip design is the back-end (physical
design) effort. We propose a complete design infrastructure
to physically implement an asynchronous digital netlist with
orders of magnitude time savings over expert human effort.
The core of this flow is the ability to generate customized logic
that is compatible with available ASIC flows. We evaluate our
flow against several asynchronous circuit benchmarks for which
full custom physical implementations exist. Compared to handoptimized
custom designs, our flow produces layout that has, on
average, a 51% area overhead, with a 12% increase in energy
and a 9% increase in delay.
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