Handouts

Background Info

• The labs for this class will use a Linux (a flavor of Unix) environment. If you are unfamiliar with the Unix environment, there is a concise online tutorial to help get you started. There are a few differences between the environment we will be using in class and the one described in the tutorial, so use this tutorial as a way to learn common commands; in other words, don't take everything literally. For example,
  • If you are using the docker container, your initial user name is "user" (not "ee91ab" as in their example)
  • The path names will be different from the ones described in the tutorial, but the concepts are the same
  • Some of the files they ask you to copy (Tutorial 2) don't exist (/vol/example/...)
  • It may be easier to just look at the summary of commands at the end of each tutorial
  • The default shell is bash on Linux
• Although Makefiles can have frustrating syntax, they are extremely useful. Ordinarily Makefiles are presented as tools for software development, but they can be used for any purpose. Examples of writing Makefiles for software development are available online (see section 2.2 for an example). Since chip development involves manipulating files in various formats, Makefiles are useful in ensuring that changes to one file are propagated through the design flow.

The tools we will be using in the class have been used for chip design have been developed by a combination of academic researchers and industry. Most of them have documentation online, and if you like you can also download their source and compile them yourselves.

• The magic VLSI layout editor
• The irsim switch-level circuit simulator

The design rules we will be using were developed when technology scaling obeyed the ideal scaling rules. The technology we will be using for the class is representative of a 0.18μm feature size, and so we will be using the scalable CMOS deep submicron rules.

• Magic technology name: SCN6M_DEEP.09 (6 metal layer, deep submicron rules, λ=0.09μm)
• ACT technology name: g180 (for generic 180nm)
• IRSIM parameter file: g180.prm
• Design rules. This file describes the design rules for the three variants of scalable CMOS rules: the original scalable rules, the rules introduced for sub-micron processes, and the rules for deep submicron processes (used for the class).