Asynchronous VLSI and Architecture
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Asynchronous Computer Architecture

    
ULSNAP processor      ULSNAP with real-time current profile


What are the implications of abandoning a global clock on computer architecture? Difficulties with global clock distribution have led researchers to propose several alternatives to globally clocked circuits. Globally asynchronous/locally synchronous (GALS) and locally asynchronous/globally synchronous (LAGS) circuits are two options being considered by other researchers.

My group investigates the case when no clocks are used in the entire design. The results of this work can be used as-is, or in conjunction with partially clocked designs (GALS, LAGS) that contain asynchronous components. We are currently investigating energy and performance characteristics of components in asynchronous architectures.

We are also investigating the impact of 3D integration on system architecture. This raises some new issues that involve thermal management, interconnect scaling, and system organization.

A more detailed description as to why we consider this an interesting approach is provided in the paper A Case for Asynchronous Computer Architecture listed below.

Collaborators

Abhishek Bhattacharjee


Participants

Ruslan Dashkin
Xiayuan Wen

Alums

David Biermann (Ph.D. 2006)
Edward Bingham (Ph.D. 2020)
David Fang (Ph.D. 2008)
Ioannis Karageorgos (Ph.D. 2017 KU Leuven)
Julia Karl (M.S. 2015)
Chris LaFrieda (Ph.D. 2009)
Tayyar Rzayev (Ph.D. 2020)
Basit Riaz Sheikh (Ph.D. 2011)
Nitish Srivastava (Ph.D. 2020)

Publications

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé. Zerializer: Towards Zero-Copy Serialization. 18th Workshop on Hot Topics in Operating Systems (HotOS), May/June 2021. (abstract, pdf)

Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf)

Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf)   — IEEE Micro Top Picks

Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141 (TVLSI), September 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf)

Ned Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 (TVLSI), January 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf)

Sandra Jackson and Rajit Manohar. Gradual Synchronization. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016. (abstract, pdf)   — Best paper nominee

Rajit Manohar. Comparing Stochastic and Deterministic Computing. IEEE Computer Architecture Letters, 14(2):119--122, July 2015. (abstract, pdf)   — Best of Computer Architecture Letters

Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar. Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices with Bi-Stable Displays. Proceedings of the ACM CHI Conference on Human Factors in Computing Systems (CHI), April 2014. (abstract, pdf)

Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes. Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2014. (abstract, pdf)

François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar. An Asymmetric Dual-Processor Architecture for Low Power Information Appliances. ACM Transactions on Embedded Computing Systems, 13(4), February 2014. (abstract, pdf)

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf)

Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf)   — Best paper award

Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2005. (abstract, pdf, ps)   — Best paper nominee

Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps)   — Best paper award

Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (abstract, pdf, ps)

David Biermann, Emin Gun Sirer, and Rajit Manohar. A Rate Matching-based Approach to Dynamic Voltage Scaling. Proceedings of the First Watson Conference on the Interaction between Architecture, Circuits, and Compilers, October 2004. (abstract, pdf, ps)

David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps)

Clinton Kelly IV and Rajit Manohar. An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. Seventh IEEE International Symposium on Distributed Simulation and Real Time Applications, October 2003. (abstract, pdf, ps)

Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 24--33, Vancouver, BC, May 2003. (abstract, pdf, ps)

Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps)

Rajit Manohar and Clinton Kelly IV. Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI. IEEE Communications Magazine, pp. 149--155, November 2001. (abstract, pdf, ps)

Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, pdf, ps)

Rajit Manohar, Mika Nyström, and Alain J. Martin. Precise Exceptions in Asynchronous Processors. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 16--28, Salt Lake City, Utah, March 2001. (abstract, pdf, ps)

Rajit Manohar. A Case for Asynchronous Computer Architecture. Proceedings of the ISCA Workshop on Complexity-Effective Design, June 2000. (abstract, pdf, ps)

Rajit Manohar and Mark Heinrich. A Case For Asynchronous Active Memories. ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000. (abstract, ps)


 
  
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