Asynchronous VLSI and Architecture
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Publications organized by research area are listed with pages describing the area. Note that publications are provided here only to ensure timely dissemination of technical work on a non-commercial basis. Copyright are maintained by the authors or by other copyright holders. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

[Papers]  [Theses]  [Reports]
Refereed Papers:

Neuromorphic Computing [click to toggle all vs five]

Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf)

Saber Moradi and Rajit Manohar. The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. To appear, Journal of Physics D: Applied Physics, 52(1), Special issue on brain-inspired pervasive computing: from materials to neuromorphic architectures/applications, October 2018. (abstract, pdf)

Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (abstract, pdf)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. Fractured Arithmetic Accelerator for Training Deep Neural Networks. Workshop on Hardware and Algorithms for On-chip Learning, International Conference on Computer-Aided Design (ICCAD), November 2016.

Design Methodology and Automation [click to toggle all vs five]

Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a digital flow for asynchronous VLSI systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.    — 2nd place, best open-source tool

Samira Ataei, Rajit Manohar. A unified memory compiler for synchronous and asynchronous circuits. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.    — 3rd place, best open-source tool

Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. International Conference on Computer-Aided Design (ICCAD), November 2019.

Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. Work-in-progress session, Design Automation Conference, June 2019.

Rajit Manohar and Yoram Moses. Asynchronous Signalling Processes. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019. (abstract, pdf)

Energy-efficient VLSI and Arithmetic [click to toggle all vs five]

Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a digital flow for asynchronous VLSI systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.    — 2nd place, best open-source tool

Samira Ataei, Rajit Manohar. A unified memory compiler for synchronous and asynchronous circuits. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.    — 3rd place, best open-source tool

Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141, September 2019. (pdf)

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809, April 2019. (abstract, pdf)

Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf)

Asynchronous FPGAs [click to toggle all vs five]

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.

Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf)

Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper finalist

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Ultra Low Power Embedded Systems [click to toggle all vs five]

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf)

Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. AES Hardware-Software Co-Design in WSN. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf)

Benjamin Tang, Sunil Bhave, and Rajit Manohar. Low Power Asynchronous VLSI with NEM Relays. Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014. (abstract, pdf)   — Best paper finalist

Asynchronous Computer Architecture [click to toggle all vs five]

Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141, September 2019. (pdf)

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809, April 2019. (abstract, pdf)

Edward Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 , January 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Three Dimensional Integration [click to toggle all vs five]

Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf)

T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract)

S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.

Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf)

David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf)

Resilient Asynchronous Systems [click to toggle all vs five]

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf)

Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.

Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.

Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf)

Theses:

Ph.D.
Tayyar Rzayev. Architectures for Intelligent Information Systems. Ph.D. thesis, May 2019.

Benjamin Hill. Architecture and Synthesis for Dynamically Reconfigurable Asynchronous FPGAs. Ph.D. thesis, December 2015.

Robert Karmazin. Automating the Physical Design of Asynchronous Circuits. Ph.D. thesis, November 2015.

Jonathan Tse. A Study of Asynchronous Links and Logic. Ph.D. thesis, October 2015.

Stephen Longfield. Constructive Verification of Quasi Delay-Insensitive Circuits. Ph.D. thesis, March 2015.

Carlos Tadeo Ortega Otero. Asynchronous Design for Ubiquitous Computing. Ph.D. thesis, July 2014.

Sandra Jackson. Gradual Synchronization. Ph.D. thesis, July 2014.

Nabil Imam. Canonical Neural Computations in Asynchronous Neuromorphic Circuits. Ph.D. thesis, April 2014.

Benjamin Zhong Xian Tang. Exploiting Asynchrony in GPS Receiver Systems to Enable Ultra-Low-Power Operation. Ph.D. thesis, January 2014.

Basit Riaz Sheikh. Operand-Optimized Asynchronous Floating-Point Arithmetic. Ph.D. thesis, August 2011.

Filipp Akopyan. Hybrid Synchronous/Asynchronous Design. Ph.D. thesis, April 2011.

Christopher LaFrieda. Relaxed Quasi Delay-Insensitive Circuits. Ph.D. thesis, December 2009.

David Fang. A Profiling Infrastructure for Performance Evaluation of Asynchronous Systems. Ph.D. thesis, May 2008.

David Biermann. A Workload Adaptive Voltage Scaling Multiple Clock Domain Architecture. Ph.D. thesis, September 2006.

Song Peng. Implementing Self-Healing Behavior in Quasi Delay-Insensitive Circuits. Ph.D. thesis, August 2006.

Clinton Kelly, IV. The Design and Implementation of an Asynchronous Network on a Chip. Ph.D. thesis, July 2005.

Virantha Ekanayake. Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Ph.D. thesis, May 2005.

John Teifel. Fast Prototyping of Asynchronous Logic. Ph.D. thesis, August 2004.

M.S.
Yuan Tian. A Parallel Implementation of Hierarchical Belief Propagation. M.S. thesis, May 2013.

Stephen Longfield. Design and Implementation of a Low Power Asynchronous GPS Baseband Processor. M.S. thesis, March 2013.

Carlos Tadeo Ortega Otero. Static Power Reduction Techniques for Asynchronous Circuits. M.S. thesis, May 2012.

Nabil Imam. A Communication Infrastructure for Multi-Chip Neuromorphic Systems. M.S. thesis, May 2012.

Christopher LaFrieda. Custom-Quality Wire Routing Using Modern Design Rules. M.S. thesis, August 2005.

Filipp Akopyan. Asynchronous Analog-to-Digital Converter for Low Power Applications. M.S. thesis, August 2005.

David Fang. Width-Adaptive and Non-Uniform Access Asynchronous Register Files. M.S. thesis, January, 2004.

Clinton Kelly, IV. Wireless Network Simulation Done Faster than Real Time. M.S. thesis, January, 2003.

Virantha Ekanayake. Asynchronous Dynamic Random Access Memories. M.S. thesis, January, 2003.

David Biermann. Multiprocessor-Enabled Asynchronous Cache Controller. M.S. thesis, January 2003.

John Teifel. Interchip Communication in Asynchronous VLSI Systems. M.S. thesis, May 2002.

Other Technical Reports:

Rajit Manohar and Alain J. Martin. Pipelined Mutual Exclusion and the Design of an Asynchronous Microprocessor. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1017, November 2001.

Rajit Manohar and Mika Nyström. Implications of Voltage Scaling in Asynchronous Architectures. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1013, April 2001.

Rajit Manohar and Mark Heinrich. The Branch Processor Architecture. Cornell Computer Systems Lab Technical Report CSL-TR-1999-1000, November 1999.

Rajit Manohar. Variable-Precision Number Representations for Asynchronous VLSI. Cornell Computer Systems Lab Technical Report CSL-TR-1999-999, September 1999.

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12.


 
  
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