Asynchronous VLSI and Architecture
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Publications organized by research area are listed with pages describing the area. Note that publications are provided here only to ensure timely dissemination of technical work on a non-commercial basis. Copyright are maintained by the authors or by other copyright holders. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

[Papers]  [Theses]  [Reports]
Refereed Papers:

Neuromorphic Computing [click to toggle all]

Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (pdf)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Design Methodology and Automation [click to toggle all]

Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216, January 2018. (abstract, pdf)

Asa Dan, Rajit Manohar, and Yoram Moses. On Using Time Without Clocks via Zigzag Causality. ACM Symposium on Principles of Distributed Computing (PODC), July 2017. (pdf)

Rajit Manohar and Yoram Moses. The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2017. (abstract, pdf)   — Best paper finalist

Nitish Srivastava, Steve Dai, Rajit Manohar, and Zhiru Zhang. Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. Proc. ACM Symposium on Field-Programmable Gate Arrays (FPGA), February 2017. (abstract, pdf)

Energy-efficient VLSI and Arithmetic [click to toggle all]

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf)

Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf)

Asynchronous FPGAs [click to toggle all]

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Ultra Low Power Embedded Systems [click to toggle all]

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf)

Asynchronous Computer Architecture [click to toggle all]

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf)

Three Dimensional Integration [click to toggle all]

Resilient Asynchronous Systems [click to toggle all]

Theses:

Ph.D.
Benjamin Hill. Architecture and Synthesis for Dynamically Reconfigurable Asynchronous FPGAs. Ph.D. thesis, December 2015.

Robert Karmazin. Automating the Physical Design of Asynchronous Circuits. Ph.D. thesis, November 2015.

Jonathan Tse. A Study of Asynchronous Links and Logic. Ph.D. thesis, October 2015.

Stephen Longfield. Constructive Verification of Quasi Delay-Insensitive Circuits. Ph.D. thesis, March 2015.

Carlos Tadeo Ortega Otero. Asynchronous Design for Ubiquitous Computing. Ph.D. thesis, July 2014.

Sandra Jackson. Gradual Synchronization. Ph.D. thesis, July 2014.

Nabil Imam. Canonical Neural Computations in Asynchronous Neuromorphic Circuits. Ph.D. thesis, April 2014.

Benjamin Zhong Xian Tang. Exploiting Asynchrony in GPS Receiver Systems to Enable Ultra-Low-Power Operation. Ph.D. thesis, January 2014.

Basit Riaz Sheikh. Operand-Optimized Asynchronous Floating-Point Arithmetic. Ph.D. thesis, August 2011.

Filipp Akopyan. Hybrid Synchronous/Asynchronous Design. Ph.D. thesis, April 2011.

Christopher LaFrieda. Relaxed Quasi Delay-Insensitive Circuits. Ph.D. thesis, December 2009.

David Fang. A Profiling Infrastructure for Performance Evaluation of Asynchronous Systems. Ph.D. thesis, May 2008.

David Biermann. A Workload Adaptive Voltage Scaling Multiple Clock Domain Architecture. Ph.D. thesis, September 2006.

Song Peng. Implementing Self-Healing Behavior in Quasi Delay-Insensitive Circuits. Ph.D. thesis, August 2006.

Clinton Kelly, IV. The Design and Implementation of an Asynchronous Network on a Chip. Ph.D. thesis, July 2005.

Virantha Ekanayake. Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Ph.D. thesis, May 2005.

John Teifel. Fast Prototyping of Asynchronous Logic. Ph.D. thesis, August 2004.

M.S.
Yuan Tian. A Parallel Implementation of Hierarchical Belief Propagation. M.S. thesis, May 2013.

Stephen Longfield. Design and Implementation of a Low Power Asynchronous GPS Baseband Processor. M.S. thesis, March 2013.

Carlos Tadeo Ortega Otero. Static Power Reduction Techniques for Asynchronous Circuits. M.S. thesis, May 2012.

Nabil Imam. A Communication Infrastructure for Multi-Chip Neuromorphic Systems. M.S. thesis, May 2012.

Christopher LaFrieda. Custom-Quality Wire Routing Using Modern Design Rules. M.S. thesis, August 2005.

Filipp Akopyan. Asynchronous Analog-to-Digital Converter for Low Power Applications. M.S. thesis, August 2005.

David Fang. Width-Adaptive and Non-Uniform Access Asynchronous Register Files. M.S. thesis, January, 2004.

Clinton Kelly, IV. Wireless Network Simulation Done Faster than Real Time. M.S. thesis, January, 2003.

Virantha Ekanayake. Asynchronous Dynamic Random Access Memories. M.S. thesis, January, 2003.

David Biermann. Multiprocessor-Enabled Asynchronous Cache Controller. M.S. thesis, January 2003.

John Teifel. Interchip Communication in Asynchronous VLSI Systems. M.S. thesis, May 2002.

Other Technical Reports:

Rajit Manohar and Alain J. Martin. Pipelined Mutual Exclusion and the Design of an Asynchronous Microprocessor. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1017, November 2001.

Rajit Manohar and Mika Nyström. Implications of Voltage Scaling in Asynchronous Architectures. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1013, April 2001.

Rajit Manohar and Mark Heinrich. The Branch Processor Architecture. Cornell Computer Systems Lab Technical Report CSL-TR-1999-1000, November 1999.

Rajit Manohar. Variable-Precision Number Representations for Asynchronous VLSI. Cornell Computer Systems Lab Technical Report CSL-TR-1999-999, September 1999.

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12.


 
  
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