Differences

This shows you the differences between two versions of the page.

--- asic:timing:graph [2024/03/22 05:58]
rajit [Datapath logic]
+++ asic:timing:graph [2024/03/29 06:13]
rajit [Timing model and graph]
@@ Line 11: / Line 11: @@
 {{ :asic:timing:invring2.png?200 | inverter ring}}
-What happens if we make one of the ring oscillators slower? The C-element will wait for the //slower// of the two oscillators before changing its output. Hence, the cycle period of this particular circuit will be determined by the slowest cycle of gates in the circuit. This simple example and intuition can be translated into a [[https://csl.yale.edu/~rajit/abstracts/exactmulti.html|rigorous mathematical framework]], where we can show that an asynchronous circuit will exhibit periodic behavior.((S.M. Burns and A.J. Martin. Performance Analysis and Optimization of Asynchronous Circuits. Proc. ARVLSI, 1991.))((Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018.))
+What happens if we make one of the ring oscillators slower? The C-element will wait for the //slower// of the two oscillators before changing its output. Hence, the cycle period of this particular circuit will be determined by the slowest cycle of gates in the circuit. This simple example and intuition can be translated into a [[https://csl.yale.edu/~rajit/abstracts/exactmulti.html|rigorous mathematical framework]], where we can show that an asynchronous circuit will exhibit periodic behavior((S.M. Burns and A.J. Martin. Performance Analysis and Optimization of Asynchronous Circuits. Proc. ARVLSI, 1991.))((Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018.)) and that the period is determined by the //slowest// cycle of gates that oscillate.
 ===== From gates to events =====
@@ Line 95: / Line 95: @@
 ===== Why tick edges at all? =====
-If a timing graph has a cycle of arcs with no ticks, this corresponds to an asynchronous circuit that is deadlocked--i.e. that does not oscillate. If this is detected, Cyclone will report an unticked cycle and display the cyclic path in the timing that is problematic.
+If a timing graph has a cycle of arcs with no ticks, this corresponds to an asynchronous circuit that is deadlocked--i.e. that does not oscillate. If this is detected, Cyclone will report an unticked cycle and display the cyclic path in the timing that is problematic and then stop.
 ===== When all else fails... =====