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asic:start [2023/11/23 12:04]
rajit
asic:start [2023/11/23 12:14] (current)
rajit
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    * [[asic:cells:|Mapping production rules to a cell library]]    * [[asic:cells:|Mapping production rules to a cell library]]
-   * [[asic:placement:|Placement]] +   * [[asic:pnr:|Place and route]]
-   * [[asic:routing:|Routing]]+
  
 In addition, [[asic:timing:|timing analysis]] can be used to estimate the performance of the design, as well as check timing constraints. In addition, [[asic:timing:|timing analysis]] can be used to estimate the performance of the design, as well as check timing constraints.
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 All of these parts are integrated into the ''interact'' tool that is part of the ASIC flow repository. All of these parts are integrated into the ''interact'' tool that is part of the ASIC flow repository.
  
-===== Placement and routing ===== 
  
-Once the routed cell library ''.rect'' files are ready, using the same script as above will create a layout problem for place and route that includes the correct LEF for the cells. 
  
-The next step is to run the [[https://ieeexplore.ieee.org/document/9256795|placement engine]] called ''dali''. To do so, continue with the following ''interact'' commands: 
- 
-<code> 
-interact> dali:init 3 
-interact> dali:place-design 0.6 
-interact> dali:place-io "met1" 
-interact> dali:export-phydb 
-interact> dali:close 
-interact> phydb:write-aux-rect "output" 
-interact> phydb:update-lef "output" 
-interact> 
-</code> 
- 
-The first  command initializes the placement engine. The ''3'' is the verbosity level (0 turns off verbose messages).  The next command runs the global and detailed placer, with a placement density of ''0.6''. Note that you should have provided sufficient area in the ''phydb:create'' command, otherwise this will fail. The next command places the I/O pins on metal1 in an automated fashion. ("met1" comes from the name for metal1 in the sky130l technology file.) Finally, the placed results are used to update the physical database, and the placement engine is terminated. 
- 
-The last two commands are required because Dali uses a gridded  cell placement approach. This means that wells and selects have to be superimposed once the gridded cell placement is complete. Hence, the LEF file needs to be updated to include these new parts of the design. 
- 
-At any point, you can see the current state of the DEF file using: 
-<code> 
-interact> phydb:write-def "file.def" 
-interact> 
-</code> 
- 
-This flow corresponds to a gridded placement flow. For gridded cells, the power buses are run after placement. To run this special power bus router, use the following commands: 
-<code> 
-interact> pwroute:init 3 
-interact> pwroute:set_reinforcement 0 
-interact> pwroute:run 
-interact> pwroute:export-phydb 
-interact> pwroute:close 
-interact> 
-</code> 
-Here we turn off reinforcements, as the technology does not have many metal layers. For a more modern process, the power router is capable of adding horizontal and vertical reinforcements of the power grid as well. 
- 
-Finally, we can run the global router called ''sproute'' as follows: 
-<code> 
-interact> sproute:init 3 
-interact> sproute:run 
-interact> sproute:close 
-interact> 
-</code> 
- 
-The routing guide file can be saved using 
-<code> 
-interact> phydb:write-guide "output.guide" 
-interact> 
-</code> 
- 
-This contains the global routing guide that can be read by a number of open source tools (e.g. TritonRoute, which is installed as part of the actflow repo) to complete the detailed routing. For example, the command 
-<code> 
-$ TritonRoute -lef output.lef -def output.def -guide output.guide -output routed 
-</code> 
-would run detailed routing, saving the result to ''routed.def''. 
- 
- 
-===== Timing analysis ===== 
- 
-Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works. 
- 
-   * [[asic:timing:graph|Timing model and graph]] 
-   * [[asic:timing:cells|Cell library and characterization]] 
-   * [[asic:timing:constraints|Timing constraints]] 
- 
-===== Power analysis =====