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--- asic:start [2023/11/23 12:06]
rajit
+++ asic:start [2023/11/23 12:14] (current)
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-===== Timing analysis =====
-Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works.
-   * [[asic:timing:graph|Timing model and graph]]
-   * [[asic:timing:cells|Cell library and characterization]]
-   * [[asic:timing:constraints|Timing constraints]]
-===== Power analysis =====