Differences

This shows you the differences between two versions of the page.

--- asic:start [2023/11/23 17:06] – rajit
+++ asic:start [2023/11/23 17:14] (current) – rajit
@@ Line 47: / Line 47: @@
-===== Timing analysis =====
-Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works.
-   * [[asic:timing:graph|Timing model and graph]]
-   * [[asic:timing:cells|Cell library and characterization]]
-   * [[asic:timing:constraints|Timing constraints]]
-===== Power analysis =====