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| asic:timing:cells [2023/11/18 20:53] – rajit | asic:timing:cells [2024/05/31 18:37] (current) – rajit |
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| For combinational gates, there is no difference in the ''.lib'' format that Cyclone expects compared to standard clocked timing analysis tools. However, since asynchronous circuits use numerous state-holding gates, we represent them differently in the ''.lib'' file compared to the mechanism provided in the Liberty file format. In particular, we represent state-holding gates in the same way as combinational gates are represented. The only difference is that the ''function:'' field in the cell definition uses a feedback loop (the output of the gate is included in the logic equation for the gate) to represent the state-holding gate functionality. For example, a C-element | For combinational gates, there is no difference in the ''.lib'' format that Cyclone expects compared to standard clocked timing analysis tools. However, since asynchronous circuits use numerous state-holding gates, we represent them differently in the ''.lib'' file compared to the mechanism provided in the Liberty file format. In particular, we represent state-holding gates in the same way as combinational gates are represented. The only difference is that the ''function:'' field in the cell definition uses a feedback loop (the output of the gate is included in the logic equation for the gate) to represent the state-holding gate functionality. For example, a C-element |
| <code> | <code act> |
| a & b -> c- | a & b -> c- |
| ~a & ~b -> c+ | ~a & ~b -> c+ |
| would correspond to the function | would correspond to the function |
| <code> | <code> |
| function: "~a & ~b | ~(a&b)&c" | function: "!a*!b + c*!(a*b)" |
| </code> | </code> |
| | We use the same approach for latches as well. |
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| | The [[https://github.com/asyncvlsi/actflow|actflow]] repository includes [[https://csl.yale.edu/~rajit/ps/xcell.pdf|''xcell'']], which is a [[asic:timing:xcell:start|cell library characterization tool]] that generates ''.lib'' files that can be handled by Cyclone. The tool takes a list of ACT cell definitions and runs a large number of SPICE simulations to compute delay and power tables. |
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