Cell library and characterization

Cells in the ACT flow are identified via defcell definitions. Typically all the production rules in a design will be mapped to cells that are contained in a cells.act file, as described in the ASIC flow overview. Logic synthesis tools may, in addition, define their own cells for special components that are explicitly instantiated and defined as a defcell. For example, a logic synthesis flow might define a single component with multiple production rules as a monolithic register. An AND gate as a cell would include two production rules (a NAND followed by an inverter), and would also have to be explicitly defined as a cell to prevent the cell mapper from factoring out each production rule into a separate cell.

Each cell in the design needs to be characterized so that Cyclone can determine their delays during timing analysis. The characterized cell delays are saved in the industry-standard Liberty (.lib) file format. Cyclone currently only includes the NLDM delay model, so the .lib file must use this model for delays.

For combinational gates, there is no difference in the .lib format that Cyclone expects compared to standard clocked timing analysis tools. However, since asynchronous circuits use numerous state-holding gates, we represent them differently in the .lib file compared to the mechanism provided in the Liberty file format. In particular, we represent state-holding gates in the same way as combinational gates are represented. The only difference is that the function: field in the cell definition uses a feedback loop (the output of the gate is included in the logic equation for the gate) to represent the state-holding gate functionality. For example, a C-element

a & b -> c-
~a & ~b -> c+

would correspond to the function

function: "!a*!b + c*!(a*b)"

We use the same approach for latches as well.

The actflow repository includes ''xcell'', which is a cell library characterization tool that generates .lib files that can be handled by Cyclone. The tool takes a list of ACT cell definitions and runs a large number of SPICE simulations to compute delay and power tables.