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| asic:timing:cells [2023/11/18 21:00] – rajit | asic:timing:cells [2024/05/31 18:37] (current) – rajit |
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| We use the same approach for latches as well. | We use the same approach for latches as well. |
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| The [[https://github.com/asyncvlsi/actflow|actflow]] repository includes [[https://csl.yale.edu/~rajit/ps/xcell.pdf|''xcell'']], which is a cell library characterization tool that generates ''.lib'' files that can be handled by Cyclone. The tool takes a list of ACT cell definitions and runs a large number of SPICE simulations to compute delay and power tables. | The [[https://github.com/asyncvlsi/actflow|actflow]] repository includes [[https://csl.yale.edu/~rajit/ps/xcell.pdf|''xcell'']], which is a [[asic:timing:xcell:start|cell library characterization tool]] that generates ''.lib'' files that can be handled by Cyclone. The tool takes a list of ACT cell definitions and runs a large number of SPICE simulations to compute delay and power tables. |
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