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| asic:timing:graph [2026/06/15 10:55] – [Control logic and tick placement] rajit | asic:timing:graph [2026/06/15 10:58] (current) – [Datapath logic] rajit | ||
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| In the simple linear pipeline example above, none of the datapath logic would have ticked edges since the '' | In the simple linear pipeline example above, none of the datapath logic would have ticked edges since the '' | ||
| - | However, if instead we have a token ring, that token ring would have some datapath element (and the control handshake) that initializes with a token on its output and valid data in the datapath. For that particular datapath storage element, we would tick the data input to the storage element. | + | However, if instead we have a token ring with a quasi delay insensitive datapath, that token ring would have some datapath element (and the control handshake) that initializes with a token on its output and valid data in the datapath. For that particular datapath storage element, we would tick the data input to the storage element. This is similar to the scenario above where the request signal was initially high. |
| ===== Why tick edges at all? ===== | ===== Why tick edges at all? ===== | ||