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| asic:timing:graph [2024/03/22 09:58] – [Datapath logic] rajit | asic:timing:graph [2024/03/29 10:19] (current) – [How does one tick edges?] rajit | ||
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| - | What happens if we make one of the ring oscillators slower? The C-element will wait for the //slower// of the two oscillators before changing its output. Hence, the cycle period of this particular circuit will be determined by the slowest cycle of gates in the circuit. This simple example and intuition can be translated into a [[https:// | + | What happens if we make one of the ring oscillators slower? The C-element will wait for the //slower// of the two oscillators before changing its output. Hence, the cycle period of this particular circuit will be determined by the slowest cycle of gates in the circuit. This simple example and intuition can be translated into a [[https:// |
| ===== From gates to events ===== | ===== From gates to events ===== | ||
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| In the examples above, it was clear where the ticks in the timing graph should be placed. However, in a general asynchronous circuit, determining the placement of ticks after-the-fact is a non-trivial problem. | In the examples above, it was clear where the ticks in the timing graph should be placed. However, in a general asynchronous circuit, determining the placement of ticks after-the-fact is a non-trivial problem. | ||
| - | In fact, techniques for doing this that are known (e.g. described in the Cyclone paper) | + | In fact, techniques for doing this that are known (e.g. described in the Cyclone paper) |
| Placing ticks in the right location is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph. | Placing ticks in the right location is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph. | ||
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| ===== Why tick edges at all? ===== | ===== Why tick edges at all? ===== | ||
| - | If a timing graph has a cycle of arcs with no ticks, this corresponds to an asynchronous circuit that is deadlocked--i.e. that does not oscillate. If this is detected, Cyclone will report an unticked cycle and display the cyclic path in the timing that is problematic. | + | If a timing graph has a cycle of arcs with no ticks, this corresponds to an asynchronous circuit that is deadlocked--i.e. that does not oscillate. If this is detected, Cyclone will report an unticked cycle and display the cyclic path in the timing that is problematic |
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| ===== When all else fails... ===== | ===== When all else fails... ===== | ||