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--- asic:timing:graph [2024/03/29 10:13] – [Timing model and graph] rajit
+++ asic:timing:graph [2024/03/29 10:19] (current) – [How does one tick edges?] rajit
@@ Line 58: / Line 58: @@
 In the examples above, it was clear where the ticks in the timing graph should be placed. However, in a general asynchronous circuit, determining the placement of ticks after-the-fact is a non-trivial problem.
-In fact, techniques for doing this that are known (e.g. described in the Cyclone paper)  have a computational complexity that is comparable to logic synthesis. Also, they use information that is in fact computed during logic synthesis of asynchronous circuits! Hence, the ACT flow assumes that tick placement is computed and generated during the logic synthesis process. These tick specifiers are included in the [[language:langs:spec|''spec'' sub-language]].
+In fact, techniques for doing this that are known (e.g. described in the Cyclone paper)  have a computational complexity that is comparable to state-space exploration. Also, they use information that is in fact computed during logic synthesis of asynchronous circuits! Hence, the ACT flow assumes that tick placement is computed and generated during the logic synthesis process. These tick specifiers are included in the [[language:langs:spec|''spec'' sub-language]].
 Placing ticks in the right location is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph.