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--- asic:timing:xcell:start [2024/05/31 18:56] – [Cell definitions] rajit
+++ asic:timing:xcell:start [2024/06/03 16:40] (current) – [Cells with external SPICE netlists and user-defined scenarios] rajit
@@ Line 19: / Line 19: @@
 The name of the cell is ''BUFX2'', with an input signal ''A'' and
 an output signal ''Y''. Internally, the cell also has signal ''_Y'' but
-this is not exposed via its port list. The circuit is specified using the [[language:langs:prs|production rule]] syntax.
+this is not exposed via its port list. The circuit is specified using the [[language:langs:prs|production rule]] syntax, and includes a [[language:langs:sizing|sizing body]] that is used to compute the transistor sizes for the circuit.
+''xcell'' can characterize cells that are comprised of combinational gates. It can also characterize cells that include state-holding gates in a limited way. The restriction on state-holding cells is: (i) every input to a state-holding production rule in the cell is combinationally determined from the primary inputs to the cell; (ii) the output of the state-holding gate and/or its inverted version is a primary output of the cell. For these types of cells, ''xcell'' can automatically compute timing arcs that need to be characterized. Characterization entails computing a //trajectory//, which is a sequence of input changes that includes the timing arc to be characterized (details [[https://csl.yale.edu/~rajit/ps/xcell.pdf|available]]).
+For more complex cells, the user must specify the characterization trajectory in the ''xcell.conf'' configuration file.
+===== Configuration file =====
+Typically the configuration file is found in the directory where ''xcell'' is to be run, and is named ''xcell.conf''. This uses the standard ACT [[config:start#configuration_file_format|configuration file syntax]]. All parameters should be placed between a  ''begin xcell'' and ''end'' directive.
+<code>
+# example xcell configuration
+begin xcell
+# config goes here
+end
+</code>
+By default ''xcell'' assumes that ''models.sp'' exists in the ACT configuration directory for the technology. This SPICE file should include the SPICE models used for circuit simulation, along with any technology-specific option settings. A user-defined SPICE file can be used instead as follows:
+<code>
+string tech_setup "my_spice.sp"
+</code>
+This will use ''my_spice.sp'' as the SPICE deck that should be included to load all the technology information.
+<code>
+string corner "TT"
+</code>
+This specifies the process corner name to be included in the ''.lib'' file output.
+<code>
+real Vdd 1.8
+</code>
+This specifies the power supply voltage to be used during characterization.
+<code>
+real T 298
+</code>
+This specifies the temperature (in Kelvin).
+<code>
+real P_value 1.0
+</code>
+This specifies the process value for the ''.lib'' file.
+The input capacitance of a gate is characterized by computing the RC delay used to switch it. The characterization resistor is specified using the parameter below.
+<code>
+real R_value 100  # in KOhms
+</code>
+The units for the ''.lib'' file can also be specified. The example below uses microWatts for power, KOhms for resistance, picoseconds for time, etc.
+<code>
+begin units
+   real power_conv 1e-6
+   real resis_conv 1e3
+   real time_conv 1e-12
+   real cap_conv 1e-15
+   real current_conv 1e-6
+end
+</code>
+Waveforms used for characterization and transit time threshold computations for rising and falling edges are specified as below.
+<code>
+begin waveform
+   # 20% to 80%
+   real rise_low 20
+   real rise_high 80
+   real fall_high 80
+   real fall_low 20
+end
+</code>
+==== Cells with external SPICE netlists and user-defined scenarios ====
+The following is an example of a cell that needs special support for characterization.
+<code>
+begin cells
+   # the full ACT name of the cell
+   begin ::syn::var_one_bit<f>
+   # for an external netlist, uncomment the next line
+   # string spice "mycell.sp"
+   # characterization arcs
+    begin scenario
+   # scenario format
+   #   input-pin#     (0,1,...#inputs-1)
+   #   in_init_value  (0/1)
+   #   output-pin#    (0,1,...#outputs-1)
+   #   out_init_value  (0/1)
+   #   length         (2,3, or 4: length of scenario)
+   #   state1         (input truth-table format encoded as an integer)
+   #   state2
+   #   ...
+   #   stateN
+   int_table dynamic 0 0 0 0 3 2 0 1 \
+0 1 1 3 2 0 1 \
+0 0 1 3 1 0 2 \
+0 1 0 3 1 0 2
+   string_table function "wt*!wf*!Reset + !wt*!wf*!Reset*dt"  \
+                         "wf*!wt*!Reset + !wt*!wf*!Reset*df"
+   end
+   end
+end
+</code>
+The ''dynamic'' table specifies the scenarios to be run through for characterization. Each scenario corresponds to applying an input vector and running a SPICE simulation for the pre-specified amount. Scenarios can be of length 2, 3, or 4. For example, a simple combinational gate would have a scenario of length two:
+   * Step 1: apply an input vector to set the output vector to say zero.
+   * Step 2: change one of the inputs to cause the output to make a zero to one transition.
+(State-holding gates can require more complex scenarios for characterization.)
+The input vector is specified as an unsigned integer that corresponds to the values of all the input bits. The order is the same order as in the SPICE cell corresponding to subcircuit for the cell generated by ACT (e.g the same output order as you would find by running ''[[tools:netgen|prs2net]]''). To set input 0 to 1, 1 to 1, 2 to 0 would correspond to the bit pattern ''011'' (lab = bit 0), and hence the integer 3.