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| config:layout [2021/10/31 16:08] – [Vias] rajit | config:layout [2025/11/19 11:31] (current) – [Layout configuration options] rajit |
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| Note that the ''layout.conf'' file is treated specially: all parameters within it are assumed to be within a ''begin layout''/''end'' block. | Note that the ''layout.conf'' file is treated specially: all parameters within it are assumed to be within a ''begin layout''/''end'' block. |
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| | <block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** This configuration file is best written by someone who has completed some layout in the technology of interest. A design rule manual has a very large number of rules as it is supposed to cover all cases, whereas standard digital layout for cells and metal routing needs only a small subset of the rules. The ''layout.conf'' configuration file captures this subset.</block> |
| ===== General parameters ===== | ===== General parameters ===== |
| |
| int dummy_poly 0 # dummy poly | int dummy_poly 0 # dummy poly |
| int welltap_adjust 0 # welltap adjustment | int welltap_adjust 0 # welltap adjustment |
| | string gds_align "PR" # place and route boundary type for GDS |
| end | end |
| </code> | </code> |
| the well contact for n-type devices has to be moved down relative to its default generation. The ''welltap_adjust'' is set to the distance the contact for n-type transistor has to be moved down relative to its default location. | the well contact for n-type devices has to be moved down relative to its default generation. The ''welltap_adjust'' is set to the distance the contact for n-type transistor has to be moved down relative to its default location. |
| |
| | ''gds_align'' is used if GDS layers are specified. This is the GDS layer information for specifying the place and route boundary. |
| ==== Range tables ==== | ==== Range tables ==== |
| |
| This specifies the GDS layer names using ''layers'', and the corresponding major and minor layer number. When the ''gds'' section is specified, all material sections must provide two additional parameters: | This specifies the GDS layer names using ''layers'', and the corresponding major and minor layer number. When the ''gds'' section is specified, all material sections must provide two additional parameters: |
| * ''gds'', a string table of GDS layers (names) that should be generated for the abstract geometry | * ''gds'', a string table of GDS layers (names) that should be generated for the abstract geometry |
| * ''gds_bloat'', the amount the geometry should be bloated during layer generation | * ''gds_bloat'', the amount the geometry should be bloated during layer generation. If unspecified, this is taken to be zero. |
| * | * Optional items: |
| | * ''gds_mask'', a string table of GDS layers can be provided. When converting GDS layers back into abstract geometry, this mask will be used to filter out geometry when generating the abstract layer types. |
| | * ''gds_pin'', a pin layer used for metals only. This is where pins should be mapped. If unspecified, pins are mapped to the text layer (next). |
| | * ''gds_text'', a layer used for labels. If this is not specified, then the first ''gds'' layer for the material is used for labels as well. |
| | |
| For metal and via templates, the additional information is described in the template section. | For metal and via templates, the additional information is described in the template section. |
| ===== Base layer material names ===== | ===== Base layer material names ===== |
| string_table nfet "ntransistor" # fets | string_table nfet "ntransistor" # fets |
| string_table nfet_well ":ppdiff" # no pwell, but pplus diff exists | string_table nfet_well ":ppdiff" # no pwell, but pplus diff exists |
| | string_table pselect "pplus" # select layer |
| | string_table nselect "nplus" # select layer |
| end | end |
| </code> | </code> |
| * ''oppspacing'': similar to ''spacing'', except this is the minimum spacing to the opposite type of diffusion. | * ''oppspacing'': similar to ''spacing'', except this is the minimum spacing to the opposite type of diffusion. |
| * ''polyspacing'': spacing to polysilicon | * ''polyspacing'': spacing to polysilicon |
| * ''notchspacing'': if the diffusion has a notch, the spacing between the vertical edge of the notch and the edge of the polysilicon | * ''notchspacing'': if the diffusion has a notch, the spacing between the vertical edge of the notch and the edge of the polysilicon. This should be at least the ''polyspacing'' (and can be more depending on the process technology). |
| * ''overhang'': a range table that specifies the diffusion overhang depending on the width of the transistor (i.e. polysilicon) it overhangs. This is used for drawing the end of a transistor stack (sometimes called a channel-connected region). | * ''overhang'': a range table that specifies the diffusion overhang depending on the width of the transistor (i.e. polysilicon) it overhangs. This is used for drawing the end of a transistor stack (sometimes called a channel-connected region). |
| * ''via'' is a section that contains: | * ''via'' is a section that contains: |
| * ''lef_width'': if this is specified, then the LEF drawing rules for the metal layer will use this as the drawing width for routing. If it doesn't exist, then this is set to the minimum width. | * ''lef_width'': if this is specified, then the LEF drawing rules for the metal layer will use this as the drawing width for routing. If it doesn't exist, then this is set to the minimum width. |
| * ''pitch'': if this is specified, then all metal tracks are defined to snap to the specified pitch (left edge for vertical drawing, bottom edge for horizontal drawing). If unspecified, this is set to the ''lef_width'' plus minimum spacing. | * ''pitch'': if this is specified, then all metal tracks are defined to snap to the specified pitch (left edge for vertical drawing, bottom edge for horizontal drawing). If unspecified, this is set to the ''lef_width'' plus minimum spacing. |
| * The centerline for the routing tracks defined are spaced by the pitch, and the centerline is offset by ''lef_width''/2. Make sure that ''lef_width''/2 is a value that results in edges that lie on the manufacturing grid (defined in the [[config:netlist|LEF/DEF configuration section]]). Otherwise, the place and route tools will be very upset. | * The centerline for the routing tracks defined are spaced by the pitch, and the centerline is offset by ''lef_width''/2. Make sure that ''lef_width''/2 is a value that results in edges that lie on the manufacturing grid (defined in the [[config:netlist#LEF/DEF_configuration_options|LEF/DEF configuration section]]). Otherwise, the place and route tools will be very upset. |
| |
| {{ :config:metal.svg?500 | Metal design rules}} | {{ :config:metal.svg?500 | Metal design rules}} |
| int_table m1_gds_bloat 0 0 0 0 | int_table m1_gds_bloat 0 0 0 0 |
| </code> | </code> |
| | |
| | When magic technology files are auto-generted from ''layout.conf'', the standard naming conventions in magic are used (e.g. m1 = first metal layer, m2 = second metal layer, etc). When generating LEF/DEF, it is advisable to use the technology layer names used by the foundry. |
| | <code> |
| | string m1_lefname "FoundryM1Name" |
| | </code> |
| | This will use ''FoundryM1Name'' in the LEF output produced for cells, even though the magic layout layer name will remain ''m1''. |
| | |
| ===== Vias ===== | ===== Vias ===== |
| |
| * ''surround'' section, containing | * ''surround'' section, containing |
| * ''up'': minimum surround on the upper layer | * ''up'': minimum surround on the upper layer |
| * ''asym_up'': minimum surround on two opposite sides; if this is different (and larger) than ''up'', then this corresponds to having an asymmetric contact. If this is equal to ''up'', then it corresponds to a symmetric contact. | * ''asym_up'': minimum surround on two opposite sides; if this is different (and larger) than ''up'', then this corresponds to having an asymmetric contact. |
| * ''dn'': minimum surround on the lower layer | * ''dn'': minimum surround on the lower layer |
| * ''asym_dn'': similar to ''asym_up'' for the lower layer | * ''asym_dn'': similar to ''asym_up'' for the lower layer |
| * Setting both ''asym_up'' and ''asym_dn'' to zero implies that the vias have symmetric surround. | * Setting both ''asym_up'' and ''asym_dn'' to zero implies that the vias have symmetric surround, and the ''up'' and ''dn'' parameters are used to determine the surround value. If either of the ''asym'' parameters are non-zero, then we assume that we are using asymmetric vias and the ''asym'' parameters are used. |
| * ''antenna'' is a section that contains any of the following: | * ''antenna'' is a section that contains any of the following: |
| * ''ratio'': antenna ratio for this layer (default is to omit this constraint) | * ''ratio'': antenna ratio for this layer (default is to omit this constraint) |
| int_table m1_gds_bloat 0 0 0 | int_table m1_gds_bloat 0 0 0 |
| </code> | </code> |
| | |
| | ==== Vias versus Contacts ==== |
| | |
| | The ''magic'' layout editor uses the notion of a contact to simplify via generation. Contact rules in ''magic'' are normally set so that the minimum contact size can fit a via plus the overlap required on the connected materials. A magic contact can be thought of as a macro that expands into three things: the via layer, and the two materials that are connected by the via. |
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