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config:netlist [2025/08/01 17:31] – [Width and length for transistors] rajitconfig:netlist [2025/08/01 22:40] (current) – [Staticizer/keeper sizing] rajit
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 If a transistor has width W that is larger than the folding threshold F, then (W div F) transistors of width F are generated. If (W mod F) is smaller than the minimum width, then the extra width is added to the last of the (W div F) transistors; otherwise a transistor of size (W mod F) is generated as well. If a transistor has width W that is larger than the folding threshold F, then (W div F) transistors of width F are generated. If (W mod F) is smaller than the minimum width, then the extra width is added to the last of the (W div F) transistors; otherwise a transistor of size (W mod F) is generated as well.
  
 +<block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** Multi-figure devices can directly be specified in the prs body, so normally this setting is not needed and auto-folding is turned off. This can be used to bound the maximum single transistor width generated by the netlist generator. This can be useful to bound the cell height of a cell library.</block>
  
 Technologies sometimes insist that transistor lengths are fixed values. To support this, the ''discrete_length'' parameter can be set. Technologies sometimes insist that transistor lengths are fixed values. To support this, the ''discrete_length'' parameter can be set.
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 If specified, this parameter is used to increase the length of minimum length transistors in the technology when the sizing directives or production rule body turn on this feature. This is used to reduce leakage in certain technologies where the minimum length devices are extremely leaky, and need to be drawn longer in some cases. If specified, this parameter is used to increase the length of minimum length transistors in the technology when the sizing directives or production rule body turn on this feature. This is used to reduce leakage in certain technologies where the minimum length devices are extremely leaky, and need to be drawn longer in some cases.
  
 +<block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** This is rarely needed, and so by default it should be zero. In some technologies, minimum length devices are so leaky that two-input C elements don't work! Making the minimum length larger by one manufacturing grid often resolves the problem.</block>
 ==== Staticizer/keeper sizing ==== ==== Staticizer/keeper sizing ====
  
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 The ''stat'' parameters are used to size any automatically generated non-feedback inverter in a staticizer. These parameters are also used for all transistors in any combinational feedback gate. The ''stat'' parameters are used to size any automatically generated non-feedback inverter in a staticizer. These parameters are also used for all transistors in any combinational feedback gate.
  
-<block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** The transistor used for the non-weak parts of an automatically generated keeper/staticizer just need to work, so they can be smaller than the default width.</block>+<block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** The transistors used for the non-weak parts of an automatically generated keeper/staticizer just need to work, so they can be smaller than the default width to save area. If you make them too small, then the design rules for contacts dominate and the layout gets messier.</block>
  
 <code> <code>
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 In some process technologies, the foundry-provided model files include a global scale factor that applies to all width/length parameters. As a result, the netlist output generated for SPICE simulation have to be  In some process technologies, the foundry-provided model files include a global scale factor that applies to all width/length parameters. As a result, the netlist output generated for SPICE simulation have to be 
 scaled to counteract the global scale factor. ''output_scale_factor'' is used to scale the output of all width/length/area/perimeter values; the width and length are multiplied by this scale factor only when printing the SPICE output. scaled to counteract the global scale factor. ''output_scale_factor'' is used to scale the output of all width/length/area/perimeter values; the width and length are multiplied by this scale factor only when printing the SPICE output.
 +
 +<block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** The default open-source Skywater 130 SPICE models include a scale factor of 1e-6 within the SPICE model files. This means that the netlist generator in ACT has to scale up the output dimensions by 1e6 to compensate.</block>
  
 <code> <code>
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 </code> </code>
 This option is used to generate parasitic source/drain area and perimeter values for transistors. For netlists suitable for running LVS checks, this setting should be off (0). Depending on how parasitics are extracted in a particular process technology (e.g. are source/drain caps part of the model, or are they explicitly extracted), this parameter should be set to 1 (turn on area/perimeter values) or 0. This option is used to generate parasitic source/drain area and perimeter values for transistors. For netlists suitable for running LVS checks, this setting should be off (0). Depending on how parasitics are extracted in a particular process technology (e.g. are source/drain caps part of the model, or are they explicitly extracted), this parameter should be set to 1 (turn on area/perimeter values) or 0.
- 
- 
-<code> 
-real delay 500e-12 
-</code> 
-This parameter is used to convert delay units specified in timing constraints to actual time (in seconds). If unspecified, this is taken to be ''lambda'' divided by thousand, which is the standard rule of thumb for FO4 delay (assuming that ''lambda'' is half the feature size). 
  
 ===== Transistor devices ===== ===== Transistor devices =====
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 string nfet_hvt  "nhvt" string nfet_hvt  "nhvt"
 </code> </code>
-The strings above are used for the device names for each transistor type. Note that the device type names are part of the [[config:start#devices|technology-independent ACT configuration]].+The strings above are used for the device names for each transistor type. Note that the device type names are part of the [[config:generic#devices|technology-independent ACT configuration]].
  
 There are a number of parameters that are passed to transistor models that determine the width and length of the device, among other parameters. These parameters have default values that are commonly used for most technologies, but they can be modified using configuration file options. The configuration file options to do so are shown below; in the example, the parameters are set to the default value. There are a number of parameters that are passed to transistor models that determine the width and length of the device, among other parameters. These parameters have default values that are commonly used for most technologies, but they can be modified using configuration file options. The configuration file options to do so are shown below; in the example, the parameters are set to the default value.
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 This says the first device in the ''prs_device'' table is a capacitor (since ''C'' is the device string used by SPICE for capacitors). This says the first device in the ''prs_device'' table is a capacitor (since ''C'' is the device string used by SPICE for capacitors).
    
 +
 +===== Cell generation and mapping =====
 +
 +Netlists can also be generated after mapping a design to cells. The following controls the cell naming conventions.
 +
 +<code>
 +string cell_namespace "cell"
 +</code>
 +During production rule to cell mapping, the cells are all assumed to reside in a single namespace. This parameter specifies the name of this namespace.
 +
 +<code>
 +string_table cell_namemap "0n_0" "inv" \
 +                     "0n1na_01o" "nor2" \
 +                     "0n1no_01a" "nand2" \
 +                     "0n1na_01a" "celem2"
 +</code>
 +When production rules are automatically mapped to cells by the cell mapping pass, cell names are generated based on the production rule expressions for the pull-up and pull-down network. These names can get very long, and be difficult to read. This table is used to translate a generated name into something that is more understandable. The table should have an even number of entries that alternate between the generated name and the mapped name.
 +
 +<code> 
 +string cell_inport "in"
 +string cell_outport "out"
 +</code>
 +When cells are generated, their ports are called ''in'' and ''out''. This can be changed to any port name using these configuration file options.
  
 ===== Interactions with the layout editor Magic ===== ===== Interactions with the layout editor Magic =====
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 string_table ext_map "nfet_svt" "pfet_svt" string_table ext_map "nfet_svt" "pfet_svt"
 </code> </code>
-The first line maps the extract file device types to nfet or pfet (for n-type and p-type transistors). The order of this table should match the numbering of the transistors used by the ''magic'' extractor. Finally, the device names are translated into the appropriate abstract ACT device name using the ''ext_map'' table. The actual SPICE device names are generated using the defined mapping between ACT device names and  [[config:netlist#Transistor device names|technology-dependent transistor device names]].+The first line maps the extract file device types to nfet or pfet (for n-type and p-type transistors). The order of this table should match the numbering of the transistors used by the ''magic'' extractor. Finally, the device names are translated into the appropriate abstract ACT device name using the ''ext_map'' table. The actual SPICE device names are generated using the defined mapping between ACT device names and  [[config:netlist#transistor_devices|technology-dependent transistor device names]].
  
 ===== Miscellaneous ===== ===== Miscellaneous =====
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 This is used to determine the hierarchy separator when generating SPICE output. Different SPICE tools use different separators, so this can be used to customize SPICE file generation. This is used to determine the hierarchy separator when generating SPICE output. Different SPICE tools use different separators, so this can be used to customize SPICE file generation.
  
 +<block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** Xyce uses ":" as the hierarchy separator by default.</block>
  
 <code> <code>
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 If the generated circuit has more than the specified number of series transistors, a warning is generated. If the configuration parameters are either omitted or set to zero, no warnings are generated. This check is only turned on for production rules---i.e. if you specify individual transistors, those are not checked. If the generated circuit has more than the specified number of series transistors, a warning is generated. If the configuration parameters are either omitted or set to zero, no warnings are generated. This check is only turned on for production rules---i.e. if you specify individual transistors, those are not checked.
  
-<code> +
-string cell_namespace "cell" +
-</code> +
-During production rule to cell mapping, the cells are all assumed to reside in a single namespace. This parameter specifies the name of this namespace.+
  
 <code> <code>
-string_table cell_namemap "0n_0" "inv" \ +real delay 500e-12
-                     "0n1na_01o" "nor2" \ +
-                     "0n1no_01a" "nand2" \ +
-                     "0n1na_01a" "celem2"+
 </code> </code>
-When production rules are automatically mapped to cells by the cell mapping pass, cell names are generated based on the production rule expressions for the pull-up and pull-down network. These names can get very long, and be difficult to read. This table is used to translate a generated name into something that is more understandable. The table should have an even number of entries that alternate between the generated name and the mapped name.+This parameter is used to convert delay units specified in timing constraints to actual time (in seconds). If unspecified, this is taken to be ''lambda'' divided by thousand, which is the standard rule of thumb for FO4 delay (assuming that ''lambda'' is half the feature size).
  
-<code>  
-string cell_inport "in" 
-string cell_outport "out" 
-</code> 
-When cells are generated, their ports are called ''in'' and ''out''. This can be changed to any port name using these configuration file options. 
 ====== Sizing configuration options ====== ====== Sizing configuration options ======
  
config/netlist.1754069502.txt.gz · Last modified: by rajit
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