Netlist configuration options

The netlist section of the configuration file specifies transistor width defaults, and other information that controls netlist creation from production rules. The configuration file is prs2net.conf, although defaults may be specified in the ACT global configuration.

Examples of configuration file parameters are shown below. This entire set of parameters is surrounded by begin net and end, to indicate these are netlist generation parameters.

real lambda 0.03e-6

This is the scale factor used to convert to metric units from the dimensionless transistor sizes.

Device generation and parameters

int  std_p_width  10
int  std_p_length 2

int  std_n_width  5
int  std_n_length 2

The std parameters are used as default widths and lengths for production rules that do not have any sizes specified.

int  stat_p_width 5
int  stat_p_length 2

int  stat_n_width 4
int  stat_n_length 2

The stat parameters are used to size any automatically generated non-feedback inverter in a staticizer. These parameters are also used for all transistors in any combinational feedback gate.

int  min_width  4
int  min_length 2

These are global parameters indicating the minimum width/length for the technology.

int  max_n_width  300
int  max_p_width  300

These are global parameters indicating the maximum width of an n-fet and p-fet. Very wide gates don't work as you might expect due to resistive poly. This is used to enforce a limit (default is zero, which is the same as no limit) and force a user to fold very wide gets.

int fold_pfet_width 0
int fold_nfet_width 0

This is used as a width threshold to trigger folding of transistors (0 = no auto folding). Extra fingers are automatically generated with this option. The parameter specifies a folding threshold F. Transistors with width larger than F are converted into multiple fingers. If a transistor has width W that is larger than the folding threshold F, then (W div F) transistors of width F are generated. If (W mod F) is smaller than the minimum width, then the extra width is added to the last of the (W div F) transistors; otherwise a transistor of size (W mod F) is generated as well.

Technologies sometimes insist that transistor lengths are fixed values. To support this, the discrete_length parameter can be set.

int discrete_length 2

This specifies that all transistor lengths should be 2 lambda. In the scenario when the netlist requires a longer transistor (e.g. weak feedback in a staticizer), prs2net will automatically break up the long transistor into a series chain of transistors that have the equivalent effective length (rounding up in case the required width is not a multiple of discrete_length).

A technology may have only some length ranges that are valid for transistors. In this case, the fet_length_ranges parameter can be set.

int_table fet_length_ranges 2 8 10 16

This specifies that fet lengths must be in the range [2,8] or [10,16]. The ranges are assumed to be sorted by length value. Transistors that fit into a valid length range are permitted; otherwise, a series chain of transistors are generated whose cumulative length is equal to the length specified. The largest length that is smaller than the one specified is used to discretize the length.

int fet_spacing_diffonly 8
int fet_spacing_diffcontact 12
int fet_diff_overhang 10

These are used to estimate the source/drain area and perimeter in the transistors. The fet_spacing_diffonly is used for the spacing between two fets in the same diffusion stack that have no intervening diffusion contact. The fet_spacing_diffcontact is used when there is an internal contact (not used right now). The fet_diff_overhang parameter is used when the node is a primary output (used to model the edge of the stack; this also not fully utilized right now when a stack gets cut into multiple stacks).

real p_n_ratio 2.5
real weak_to_strong_ratio 0.1

The p_n_ratio is the strength ratio of n-transistors to p-transistors. The weak_to_strong_ratio says that the strength of weak feedback (auto-generated staticizers) should be 0.1 times the strength of the opposing network.

The weak feedback inverter is generated by using this strength ratio. The inverter is weakened by using a minimum size inverter with a long series transistor whose gate is connected to a constant value (essentially a series resistor). The default signal used is the local power supply for the prs block. (When a local power supply is not specified, the default signal names used are Vdd and GND.)

int disable_keepers 0

When set to 1, this option turns off automatic staticizer/keeper generation.

int comb_feedback 0

When set to 1, this option makes combinational feedback the default staticizer/keeper style.

real leakage_adjust 10e-9

If specified, this parameter is used to increase the length of minimum length transistors in the technology when the sizing directives or production rule body turn on this feature. This is used to reduce leakage in certain technologies where the minimum length devices are extremely leaky, and need to be drawn longer in some cases.

real default_load_cap 0

This value (in fF) is added to a node whenever it appears on the RHS of a production rule (per subcircuit). This can be used to “pessimize” your spice simulations to account for wiring capacitance. This can be overridden with the “loadcap=value” attribute in the production rule itself.

real unit_cap 1e-15

This value is used to specify the size of the unit capacitor used for explicit capacitors specified in the prs sublanguage. If unspecified, it is taken to be 1fF.

real delay 500e-12

This parameter is used to convert delay units specified in timing constraints to actual time (in seconds). If unspecified, this is taken to be lambda divided by thousand, which is the standard rule of thumb for FO4 delay (assuming that lambda is half the feature size).

real output_scale_factor 1

In some process technologies, the foundry-provided model files include a global scale factor that applies to all width/length parameters. As a result, the netlist output generated for SPICE simulation have to be scaled to counteract the global scale factor. output_scale_factor is used to scale the output of all width/length/area/perimeter values; the width and length are multiplied by this scale factor only when printing the SPICE output.

int emit_parasitics 0

This option is used to generate parasitic source/drain area and perimeter values for transistors. For netlists suitable for running LVS checks, this setting should be off (0). Depending on how parasitics are extracted in a particular process technology (e.g. are source/drain caps part of the model, or are they explicitly extracted), this parameter should be set to 1 (turn on area/perimeter values) or 0.

The netlist pass can be used to generate a shared staticizer structure. In this mode, one can specify that minimum and maximum number of staticizers that are permitted for a single shared weak power supply terminal.

int_table weak_sharing 2 8

This specifies that the sharing count for a weak supply is between two and eight staticizers.

Transistor device names

string pfet_svt "pch"
string pfet_lvt "plvt"
string pfet_hvt "phvt"

string nfet_svt  "nch"
string nfet_lvt  "nlvt"
string nfet_hvt  "nhvt"

The strings above are used for the device names for each transistor type. Note that the device type names are part of the technology-independent ACT configuration.

If the FET devices being used are floating-body SOI devices, then their spice representation is not of type “M” (model), but of type “X” (subcircuit). The device has the usual source, gate, drain terminals, but the fourth terminal is no longer bulk, but instead the substrate. All substrate terminals are grounded (as opposed to bulk terminals that are connected to the appropriate supply), so this requires a modified netlist. To have the “svt” device correspond to an SOI-type, use the following:

string nfet_svt "soi:nfet"
string pfet_svt "soi:pfet"

Here the fet model names are “nfet” and “pfet”, and the prefix “soi:” informs prs2net that it should always tie the fourth terminal to ground.

The use_subckt_models configuration file parameter is used to use “X” instead of “M”.

int use_subckt_models 0

The default is a 0 (which generates “M” rather than “X”).

int swap_source_drain 0

Depending on how a spice netlist needs to be used, it can be convenient to swap the source and drain nodes for all the transistors from the prs2net default.

int fin_width 4

This specifies that the netlist is for a FinFET technology, and a individual fin is equivalent to 4 units of width. All widths will be snapped to an integer multiple of the fin_width, and the transistor output will include NFIN=v that specifies the number of fins. The default is to assume a non-FinFET technology. If the value specified is zero or negative, ACT assumes a non-FinFET technology. When a FinFET technology is specified, the netlist generation process will round up all widths to be an integer multiple of fin_width. A warning will be generated if the standard and minimum widths are not an integer multiple of the fin_width since this indicates a configuration file inconsistency.

Some DRC/LVS decks require some additional parameters for transistors in the spice file. To support this, the following string is appended to any transistor line in the spice file.

string extra_fet_string ""

The default is blank, but it can be changed as necessary.

Interactions with the layout editor Magic

We typically use magic as our layout editor. To obtain device and connectivity information from physical layout, magic includes an extraction module that emits .ext format files (details are in the magic documentation). These files contain a hierarchical representation of the design which includes connectivity information and device information extracted from the physical geometry. The ACT core tools include a translator from .ext to a standard SPICE format netlist. To do this correctly, we have to map magic layers to device types.

string_table ext_devs "nfet" pfet"
string_table ext_map "nfet_svt" "pfet_svt"

The first line maps the extract file device types to nfet or pfet (for n-type and p-type transistors). The order of this table should match the numbering of the transistors used by the magic extractor. Finally, the device names are translated into the appropriate abstract ACT device name using the ext_map table. The actual SPICE device names are generated using the defined mapping between ACT device names and technology-dependent transistor device names.


string global_vdd "Vdd"
string global_gnd "GND"
string local_vdd "VddN"
string local_gnd "GNDN"

These signals are used for implicit power supplies within a netlist section. Each production rule section can specify its power and ground signals. However, if they are omitted, then the signal names specified here are used. For the power supply, first the local_vdd signal is used; if it doesn't exist, then the global_vdd signal is used. Similarly for ground.

string spice_path_sep "/"

This is used to determine the hierarchy separator when generating SPICE output. Different SPICE tools use different separators, so this can be used to customize SPICE file generation.

int series_n_warning 6
int series_p_warning 3

If the generated circuit has more than the specified number of series transistors, a warning is generated. If the configuration parameters are either omitted or set to zero, no warnings are generated. This check is only turned on for production rules—i.e. if you specify individual transistors, those are not checked.

string cell_namespace "cell"

During production rule to cell mapping, the cells are all assumed to reside in a single namespace. This parameter specifies the name of this namespace.

string_table cell_namemap "0n_0" "inv" \
                     "0n1na_01o" "nor2" \
                     "0n1no_01a" "nand2" \
                     "0n1na_01a" "celem2"

When production rules are automatically mapped to cells by the cell mapping pass, cell names are generated based on the production rule expressions for the pull-up and pull-down network. These names can get very long, and be difficult to read. This table is used to translate a generated name into something that is more understandable. The table should have an even number of entries that alternate between the generated name and the mapped name.

string cell_inport "in"
string cell_outport "out"

When cells are generated, their ports are called in and out. This can be changed to any port name using these configuration file options.

Sizing configuration options

The sizing configuration is nested within the netlist configuration, in a begin sizing/end block.

int unit_n 10

This specifies that the width of the unit n-transistor is 10 lambda wide. The default value is 5, if unspecified.

int p_n_mode 0

This specifies that the default pull-up and pull-down should be sized using the p_n_ratio netlist parameter to equalize drive strength. When set to 1, this uses different ratios more suitable for asynchronous control circuits.

int use_long_channel 0

If this is turned on, this permits the use of long channel devices when applying the sizing body. This might be needed if the width/length ratio dictates that the width of the device should be smaller than the minimum width; in this case, the specified drive strength can be achieved by using a long channel transistor.

Sizing limits

Internally, act maintains width and lengths of transistors as integer-valued variables that are a multiple of the manufacturing grid. Hence, if the ratio of lambda/manufacturing_grid is very large, then normal widths might overflow (based on the maximum integer on your system) and you might get unexpected errors. This should not be an issue in general; if the manufacturing grid is 1nm, then the maximum width and length cannot be more than 2 meters, a reasonable assumption at present.

LEF/DEF configuration options

The LEF/DEF configuration is found in the same file as the netlist configuration, in a begin lefdef/end block. Note: the LEF/DEF configuration block isn't nested within the begin net/end block for the netlist. The reason this block is included in prs2net.conf is because the manufacturing grid is used during width/length mapping.

string version "5.6"

This is used to specify the version of the LEF/DEF generated.

int micron_conversion 1000

This specifies the conversion to microns in the units section of the LEF/DEF.

real manufacturing_grid 0.001

This specifies the manufacturing grid (in microns) for the technology. Note that all transistor width and length values will snap to this manufacturing grid.

begin metal_align
  int x_dim 2
  int y_dim 1

Cells generated for gridded placement have x-size and y-size that snap to the metal grid. This specifies which metal layers are used to define the cell grid.

int horiz_metal 0

This specifies which metal layer is horizontal versus vertical. If this is 1, then odd metal layers are horizontal (metal1, metal3, etc); otherwise even metal layers are horizontal (metal2, metal4, …)

int_table routing_metal 2 5

This specifies the metal layers to be used for routing, and is used to control this in the technology LEF that is generated from the layout configuration file. (Metal layers are numbered 1, 2, etc.)

int pin_layer 2

By default, initial pin locations for cells are generated on this metal layer.

int rect_import 0

If this is set to 1, and local .rect files are found, then those files are read in to define cell geometry rather than the cell geometry being generated.

string rect_inpath "paths:tosearch/for/rect/files"
string rect_outdir "outputrectdir"

These two parameters are used to control the search path for .rect files (when rect_import is set to one) and the directory where the final output .rect files are saved, if .rect files are generated.

int rect_wells 0

This flag is used to generate explicit wells in the .rect file output. This is useful for debugging, or for checking well connectivity/plugs in the magic VLSI layout editor.

begin extra_tracks
  int top 0
  int bot 0
  int left 0
  int right 0

This parameter can be used to pad the generated cells on the top/bottom/left/right by some number of routing tracks. This can be useful for preliminary layout estimates where only a partially completed cell is available. Other uses include increasing the area used by a design to alleviate routing congestion.

int warnings 1

If this is missing or set to 1, then any warnings about default pin generation and metal layer orientation issues are displayed during layout generation. This should be set to 0 if ACT is not being used for cell generation (e.g. if you are targetting an external standard cell library).