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| config:netlist [2025/08/01 18:23] – [Transistor devices] rajit | config:netlist [2025/08/01 22:40] (current) – [Staticizer/keeper sizing] rajit |
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| The ''stat'' parameters are used to size any automatically generated non-feedback inverter in a staticizer. These parameters are also used for all transistors in any combinational feedback gate. | The ''stat'' parameters are used to size any automatically generated non-feedback inverter in a staticizer. These parameters are also used for all transistors in any combinational feedback gate. |
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| <block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** The transistor used for the non-weak parts of an automatically generated keeper/staticizer just need to work, so they can be smaller than the default width.</block> | <block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** The transistors used for the non-weak parts of an automatically generated keeper/staticizer just need to work, so they can be smaller than the default width to save area. If you make them too small, then the design rules for contacts dominate and the layout gets messier.</block> |
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| <code> | <code> |
| In some process technologies, the foundry-provided model files include a global scale factor that applies to all width/length parameters. As a result, the netlist output generated for SPICE simulation have to be | In some process technologies, the foundry-provided model files include a global scale factor that applies to all width/length parameters. As a result, the netlist output generated for SPICE simulation have to be |
| scaled to counteract the global scale factor. ''output_scale_factor'' is used to scale the output of all width/length/area/perimeter values; the width and length are multiplied by this scale factor only when printing the SPICE output. | scaled to counteract the global scale factor. ''output_scale_factor'' is used to scale the output of all width/length/area/perimeter values; the width and length are multiplied by this scale factor only when printing the SPICE output. |
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| | <block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** The default open-source Skywater 130 SPICE models include a scale factor of 1e-6 within the SPICE model files. This means that the netlist generator in ACT has to scale up the output dimensions by 1e6 to compensate.</block> |
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| <code> | <code> |
| </code> | </code> |
| This option is used to generate parasitic source/drain area and perimeter values for transistors. For netlists suitable for running LVS checks, this setting should be off (0). Depending on how parasitics are extracted in a particular process technology (e.g. are source/drain caps part of the model, or are they explicitly extracted), this parameter should be set to 1 (turn on area/perimeter values) or 0. | This option is used to generate parasitic source/drain area and perimeter values for transistors. For netlists suitable for running LVS checks, this setting should be off (0). Depending on how parasitics are extracted in a particular process technology (e.g. are source/drain caps part of the model, or are they explicitly extracted), this parameter should be set to 1 (turn on area/perimeter values) or 0. |
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| <code> | |
| real delay 500e-12 | |
| </code> | |
| This parameter is used to convert delay units specified in timing constraints to actual time (in seconds). If unspecified, this is taken to be ''lambda'' divided by thousand, which is the standard rule of thumb for FO4 delay (assuming that ''lambda'' is half the feature size). | |
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| ===== Transistor devices ===== | ===== Transistor devices ===== |
| string nfet_hvt "nhvt" | string nfet_hvt "nhvt" |
| </code> | </code> |
| The strings above are used for the device names for each transistor type. Note that the device type names are part of the [[config:generic|technology-independent ACT configuration]]. | The strings above are used for the device names for each transistor type. Note that the device type names are part of the [[config:generic#devices|technology-independent ACT configuration]]. |
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| There are a number of parameters that are passed to transistor models that determine the width and length of the device, among other parameters. These parameters have default values that are commonly used for most technologies, but they can be modified using configuration file options. The configuration file options to do so are shown below; in the example, the parameters are set to the default value. | There are a number of parameters that are passed to transistor models that determine the width and length of the device, among other parameters. These parameters have default values that are commonly used for most technologies, but they can be modified using configuration file options. The configuration file options to do so are shown below; in the example, the parameters are set to the default value. |
| This says the first device in the ''prs_device'' table is a capacitor (since ''C'' is the device string used by SPICE for capacitors). | This says the first device in the ''prs_device'' table is a capacitor (since ''C'' is the device string used by SPICE for capacitors). |
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| | ===== Cell generation and mapping ===== |
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| | Netlists can also be generated after mapping a design to cells. The following controls the cell naming conventions. |
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| | <code> |
| | string cell_namespace "cell" |
| | </code> |
| | During production rule to cell mapping, the cells are all assumed to reside in a single namespace. This parameter specifies the name of this namespace. |
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| | <code> |
| | string_table cell_namemap "0n_0" "inv" \ |
| | "0n1na_01o" "nor2" \ |
| | "0n1no_01a" "nand2" \ |
| | "0n1na_01a" "celem2" |
| | </code> |
| | When production rules are automatically mapped to cells by the cell mapping pass, cell names are generated based on the production rule expressions for the pull-up and pull-down network. These names can get very long, and be difficult to read. This table is used to translate a generated name into something that is more understandable. The table should have an even number of entries that alternate between the generated name and the mapped name. |
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| | <code> |
| | string cell_inport "in" |
| | string cell_outport "out" |
| | </code> |
| | When cells are generated, their ports are called ''in'' and ''out''. This can be changed to any port name using these configuration file options. |
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| ===== Interactions with the layout editor Magic ===== | ===== Interactions with the layout editor Magic ===== |
| This is used to determine the hierarchy separator when generating SPICE output. Different SPICE tools use different separators, so this can be used to customize SPICE file generation. | This is used to determine the hierarchy separator when generating SPICE output. Different SPICE tools use different separators, so this can be used to customize SPICE file generation. |
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| | <block 75%:0:#FFFFCC;black;1px dotted black;auto/10ptrounded>**Tip:** Xyce uses ":" as the hierarchy separator by default.</block> |
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| <code> | <code> |
| If the generated circuit has more than the specified number of series transistors, a warning is generated. If the configuration parameters are either omitted or set to zero, no warnings are generated. This check is only turned on for production rules---i.e. if you specify individual transistors, those are not checked. | If the generated circuit has more than the specified number of series transistors, a warning is generated. If the configuration parameters are either omitted or set to zero, no warnings are generated. This check is only turned on for production rules---i.e. if you specify individual transistors, those are not checked. |
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| <code> | |
| string cell_namespace "cell" | |
| </code> | |
| During production rule to cell mapping, the cells are all assumed to reside in a single namespace. This parameter specifies the name of this namespace. | |
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| <code> | <code> |
| string_table cell_namemap "0n_0" "inv" \ | real delay 500e-12 |
| "0n1na_01o" "nor2" \ | |
| "0n1no_01a" "nand2" \ | |
| "0n1na_01a" "celem2" | |
| </code> | </code> |
| When production rules are automatically mapped to cells by the cell mapping pass, cell names are generated based on the production rule expressions for the pull-up and pull-down network. These names can get very long, and be difficult to read. This table is used to translate a generated name into something that is more understandable. The table should have an even number of entries that alternate between the generated name and the mapped name. | This parameter is used to convert delay units specified in timing constraints to actual time (in seconds). If unspecified, this is taken to be ''lambda'' divided by thousand, which is the standard rule of thumb for FO4 delay (assuming that ''lambda'' is half the feature size). |
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| <code> | |
| string cell_inport "in" | |
| string cell_outport "out" | |
| </code> | |
| When cells are generated, their ports are called ''in'' and ''out''. This can be changed to any port name using these configuration file options. | |
| ====== Sizing configuration options ====== | ====== Sizing configuration options ====== |
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