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tools:actsim [2023/04/14 19:22] – [Configuration file] rajit | tools:actsim [2025/03/25 10:29] (current) – [General options] rajit | ||
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==== Timing ==== | ==== Timing ==== | ||
- | < | + | < |
Set the random timing mode and optionally specify the default random timing bounds for all nodes. | Set the random timing mode and optionally specify the default random timing bounds for all nodes. | ||
+ | If '' | ||
< | < | ||
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< | < | ||
- | turn on/off random exclhi/lo firings | + | Turn on/off random exclhi/lo firings. ACT uses '' |
- | + | This is typically used to model arbiters. If the '' | |
==== Running Simulation ==== | ==== Running Simulation ==== | ||
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{ | { | ||
adder a; | adder a; | ||
- | sim::source_seq<32, // 32-bit data | + | sim::source_sequence<32, // 32-bit data |
- | false, // don't repeat the sequence of values | + | |
3, // three data values | 3, // three data values | ||
- | {3, | + | {3,5,2}, // the data values |
+ | false, // don't repeat the sequence of values | ||
+ | 0, // source ID is zero for logging | ||
+ | false // don't log any information in the source | ||
> s1(a.A); | > s1(a.A); | ||
- | sim::source_seq<32, false, 3, {7,9,3}> s2(a.B); | + | sim::source_sequence<32, 3, {7,9,3}, false, 1, false> s2(a.B); |
- | sim:: | + | sim:: |
- | | + | 0, // sink ID for logging |
+ | true // log values | ||
> sx(a.C); | > sx(a.C); | ||
} | } | ||
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{ | { | ||
adder a; | adder a; | ||
- | // The first parameter is the file ID (default name is _infile_.0). | + | // The first parameter is the bitwidth |
- | // The second | + | // The second |
- | // The third parameter is the bit-width. | + | // The third parameter is whether the file should be looped. |
- | sim::file_source<0, false, | + | // The fourth |
+ | // The fifth parameter specifies if the source should log its output | ||
+ | sim::source_file<32, 0, false, | ||
| | ||
// This could also use a file source | // This could also use a file source | ||
- | sim::source_seq<32, false, 3, {7,9,3}> s2(a.B); | + | sim::source_sequence<32, 3, {7,9,3}, false, 1, false> s2(a.B); |
- | sim:: | + | sim:: |
- | | + | 0, // sink ID for logging |
+ | true // log values | ||
> sx(a.C); | > sx(a.C); | ||
} | } | ||
</ | </ | ||
+ | |||
+ | This example will also need a file '' | ||
===== Mixed-signal simulations ===== | ===== Mixed-signal simulations ===== | ||
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===== Configuration file ===== | ===== Configuration file ===== | ||
+ | An ACT configuration file can be read into '' | ||
+ | |||
+ | ==== General options ==== | ||
+ | |||
+ | When '' | ||
+ | < | ||
+ | begin sim | ||
+ | int reset_rounds 100 | ||
+ | end | ||
+ | </ | ||
+ | |||
+ | '' | ||
+ | < | ||
+ | begin sim | ||
+ | string sdf_file " | ||
+ | int sdf_mangled_names 1 | ||
+ | end | ||
+ | </ | ||
+ | The parameter '' | ||
==== CHP configuration options ==== | ==== CHP configuration options ==== | ||
- | The standard simulation library (in the sim namespace) uses a few configuration file settings to pick the names | + | < |
- | of the files for I/O. | + | begin sim |
+ | begin chp | ||
+ | int inf_loop_opt 0 | ||
+ | end | ||
+ | end | ||
+ | </code> | ||
+ | '' | ||
< | < | ||
- | string | + | begin sim |
+ | begin chp | ||
+ | int default_delay 0 | ||
+ | real default_leakage 0 | ||
+ | int default_area 0 | ||
+ | end | ||
+ | end | ||
</ | </ | ||
- | Change this parameter to modify | + | These set default simulation parameters for CHP processes. The default delay sets the value for each non-skip basic statement (send, receive, assignment) in a CHP program. The default |
- | Alternatively, | ||
< | < | ||
- | string_table | + | begin sim |
+ | begin chp | ||
+ | int debug_metrics 0 | ||
+ | end | ||
+ | end | ||
</ | </ | ||
- | If this parameter | + | If this is set to 1, then debugging messages are printed out showing |
- | Other simulation parameters | + | Metrics for energy, delay, leakage power, and area can be specified in a configuration file. These metrics |
< | < | ||
- | int sim.chp.inf_loop_opt 0 | + | begin sim |
+ | begin chp | ||
+ | begin mytype<> | ||
+ | begin varname | ||
+ | int D 42 | ||
+ | int E 84 | ||
+ | end | ||
+ | real leakage 1e-8 | ||
+ | int area 23 | ||
+ | end | ||
+ | end | ||
+ | end | ||
</ | </ | ||
- | '' | + | This configuration file provides annotations for energy and delay for a '' |
+ | ==== Mixed-signal simulation ==== | ||
+ | The mixed-signal simulation parameters are used to configure the interface to Xyce, and are contained in a sim.device block. | ||
< | < | ||
- | int sim.chp.default_delay 10 | + | begin sim |
+ | begin device | ||
+ | # put mixed-signal parameters here | ||
+ | end | ||
+ | end | ||
</ | </ | ||
- | This is the default delay for each non-skip basic statement (send, receive, assignment) in a CHP program. | + | The parameters are |
+ | < | ||
+ | real timescale 1e-12 | ||
+ | </ | ||
+ | This is used for the time resolution of the Xyce output trace files, if any. | ||
< | < | ||
- | int sim.chp.default_leakage 0 | + | real analog_window 0.05 |
</ | </ | ||
- | This is the default leakage associated with a process (in nW) | + | This specifies when an analog signal output should be treated as a digital 0 or digital 1. The value 0.05 means within 5% of the rail-to-rail voltage. So for a 1V power supply, this would be 0.95 for a digital 1 threshold, and 0.05 for a digital 0 threshold. |
< | < | ||
- | int sim.chp.default_area 0 | + | int case_for_sim 1 |
</ | </ | ||
- | This is the default area associated with a CHP process | + | SPICE is case-insensitive, |
< | < | ||
- | int sim.chp.debug_metrics 0 | + | real settling_time 1e-12 |
</ | </ | ||
- | If this is set to 1, then debugging messages | + | This is the settling time parameter for the built-in ADC device used to convert between the digital and analog signals. |
+ | |||
+ | < | ||
+ | int dump_all 1 | ||
+ | </ | ||
+ | If this is true, all voltage signals should be saved to the output trace file. Otherwise, only the interface signals | ||
+ | |||
+ | < | ||
+ | string output_format " | ||
+ | </ | ||
+ | This specifies which output trace file formats should be generated from the underlying analog simulation engine. Any number of colon-separated formats are supported, but only one of the built-in formats (raw, prn, etc) can be used. | ||
+ | |||
+ | < | ||
+ | int waveform_steps 10 | ||
+ | real waveform_time 10e-12 | ||
+ | </ | ||
+ | The digital input is converted to a ramp before being fed to the analog simulation. This specifies the duration and number of steps used for the conversion. | ||
+ | |||
+ | < | ||
+ | string model_files " | ||
+ | </ | ||
+ | By default, the simulation will look for the file '' | ||
+ | |||
+ | < | ||
+ | string outfile " | ||
+ | </ | ||
+ | This is the name of the trace file output that is generated. | ||
+ | |||
+ | < | ||
+ | real stop_time 100e-12 | ||
+ | </ | ||
+ | This is the time at which the trace file output should stop. | ||
+ | |||
+ | < | ||
+ | string_table measure_statements " | ||
+ | </ | ||
+ | defines additional spice lines added to each generated spice file used for the device_level simulations, you can use it for eg. recording currents measuring avergage power and so on | ||
+ | |||
+ | ==== Standard sim namespace helper functions ==== | ||
+ | |||
+ | The standard simulation library (in the sim namespace) uses a few configuration file settings to pick the names | ||
+ | of the files for I/O. | ||
+ | |||
+ | < | ||
+ | begin sim | ||
+ | begin file | ||
+ | string prefix " | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | Change this parameter to modify the default file names used by the file I/O library used by the standard simulation namespace. | ||
+ | |||
+ | Alternatively, | ||
+ | < | ||
+ | begin sim | ||
+ | begin file | ||
+ | string_table name_table " | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | If this parameter is specified, then the prefix parameter is ignored. | ||
+ |