Differences

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--- tools:actsim [2024/07/04 09:29]
rajit [Using pre-defined sources and sinks with data in the ACT file]
+++ tools:actsim [2024/08/15 14:05] (current)
rajit [Timing]
@@ Line 80: / Line 80: @@
 ==== Timing ====
-<code>random [<min> <max>]</code>
+<code>random [-u] [<min> <max>]</code>
 Set the random timing mode and optionally specify the default random timing bounds for all nodes.
+If ''-u'' is used, then randomization is only applied to unspecified delays.
 <code>random_seed <seed></code>
@@ Line 90: / Line 91: @@
 <code>random_choice on|off</code>
-turn on/off random exclhi/lo firings
+Turn on/off random exclhi/lo firings. ACT uses ''mk_exclhi'' (''mk_excllo'') [[language:langs:spec#exclusive_directives|directives]] to force signals to be exclusive-high (exclusive low).
+This is typically used to model arbiters. If the ''mk_exclhi'' (''mk_excllo'') directive is used between a set of signals, and more than one signal is driven high (low) at the same simulation time, then turning on random choice randomizes the selection of the signal that is allowed to go high (low).
 ==== Running Simulation ====
@@ Line 270: / Line 270: @@
     sim::source_sequence<32, // 32-bit data
 , // three data values
-                    {3,5,2}  // the data values
+                    {3,5,2},  // the data values
                     false, // don't repeat the sequence of values
 , // source ID is zero for logging
@@ Line 294: / Line 294: @@
 {
     adder a;
-    // The first parameter is the file ID (default name is _infile_.0).
+    // The first parameter is the bitwidth
-    // The second parameter is whether the file should be looped.
+    // The second parameter is the file ID (default name is _infile_.0).
-    // The third parameter is the bit-width.
+    // The third parameter is whether the file should be looped.
-    sim::file_source<0, false, 32> s1(a.A);
+    // The fourth parameter is the source ID for logging
+    // The fifth parameter specifies if the source should log its output
+    sim::source_file<32, 0, false, 0, false> s1(a.A);
     // This could also use a file source
-    sim::source_seq<32, false, 3, {7,9,3}> s2(a.B);
+    sim::source_sequence<32, 3, {7,9,3}, false, 1, false> s2(a.B);
-    sim::sink<true, // log output
+    sim::sink<32,  // 32-bit
-  // 32-bit
+, // sink ID for logging
+                     true // log values
               > sx(a.C);
  }