Differences

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--- tools:v2act [2025/07/25 15:42] – [Standard import mode] rajit
+++ tools:v2act [2025/07/25 16:22] (current) – [Async import mode] rajit
@@ Line 15: / Line 15: @@
 </code>
+The input Verilog netlist is assumed to be a collection of gate-level instances from a cell library. For error checking, ''v2act'' requires an ACT file that contains the library description.
 ===== Standard import mode =====
-This is the normal usage for ''v2act'', and is what occurs when the ''-a'' option is not specified. In this mode,
+This is the normal usage for ''v2act'', and is what occurs when the ''-a'' option is not specified. To understand how this works, here is a simple example of a Verilog netlist:
-the Verilog netlist is assumed to be a collection of gate-level instances from a cell library. For error checking, ''v2act'' requires an ACT file that contains the library description.  To understand how this works, here is a simple example of a Verilog netlist:
 <file verilog test.v>
@@ Line 63: / Line 63: @@
 </code>
+A few comments:
+   * Note that the instance names remain unchanged, as do port names and other signal names.
+   * The inverter is qualified by the cell library namespace.
+   * By default ''v2act'' assumes that the netlist it is importing may have switching hazards. To avoid these hazards being flagged as errors by the simulator, a ''spec'' directive indicating all signals may have hazards is included. This behavior can be toggled by using the ''-g'' command-line option to ''v2act''.
+If you don't have a complete cell definition but would still like to convert the Verilog netlist into ACT, just the declaration of each cell will suffice:
+<code act>
+namespace cell {
+defcell INVX2 (bool? A; bool! Y);
+}
+</code>
+(''v2act'' sanity checks ports, which is why this is required for translation.)
-===== Async import mode =====
+The ''actflow'' repository includes a tool called ''lib2act.py''. This is a program that can emit ACT cell declarations from a Synopsys Liberty  (''.lib'') file. This is a hack, so it may not always work (i.e. it doesn't include a real Liberty file parser and makes certain assumptions about the text layout of the ''.lib'' file) but you may find it helpful as a starting point for creating an ACT cell library from a ''.lib'' file. For example, running
+<code>
+$ lib2act.py < osu018_stdcells.lib
+</code>
+where ''osu018_stdcells.lib'' file is the 180nm open-source Liberty file provided by OSU results in the following output:
+<code>
+export defcell AND2X1 (bool? A, B; bool! Y);
+export defcell AND2X2 (bool? A, B; bool! Y);
+export defcell AOI21X1 (bool? A, B, C; bool! Y);
+export defcell AOI22X1 (bool? A, B, C, D; bool! Y);
+export defcell BUFX2 (bool? A; bool! Y);
+export defcell BUFX4 (bool? A; bool! Y);
+export defcell CLKBUF1 (bool? A; bool! Y);
+export defcell CLKBUF2 (bool? A; bool! Y);
+export defcell CLKBUF3 (bool? A; bool! Y);
+export defcell DFFNEGX1 (bool? CLK, D; bool! Q);
+export defcell DFFPOSX1 (bool? CLK, D; bool! Q);
+export defcell DFFSR (bool? CLK, D, R, S; bool! Q);
+export defcell FAX1 (bool? A, B, C; bool! YC, YS);
+export defcell HAX1 (bool? A, B; bool! YC, YS);
+export defcell INVX1 (bool? A; bool! Y);
+export defcell INVX2 (bool? A; bool! Y);
+export defcell INVX4 (bool? A; bool! Y);
+export defcell INVX8 (bool? A; bool! Y);
+export defcell LATCH (bool? CLK, D; bool! Q);
+export defcell MUX2X1 (bool? A, B, S; bool! Y);
+export defcell NAND2X1 (bool? A, B; bool! Y);
+export defcell NAND3X1 (bool? A, B, C; bool! Y);
+export defcell NOR2X1 (bool? A, B; bool! Y);
+export defcell NOR3X1 (bool? A, B, C; bool! Y);
+export defcell OAI21X1 (bool? A, B, C; bool! Y);
+export defcell OAI22X1 (bool? A, B, C, D; bool! Y);
+export defcell OR2X1 (bool? A, B; bool! Y);
+export defcell OR2X2 (bool? A, B; bool! Y);
+export defcell TBUFX1 (bool? A, EN; bool! Y);
+export defcell TBUFX2 (bool? A, EN; bool! Y);
+export defcell XNOR2X1 (bool? A, B; bool! Y);
+export defcell XOR2X1 (bool? A, B; bool! Y);
+</code>
-In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the ''-a'' option.
+===== Async import mode =====
+In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the ''-a'' option. In this mode, by default, all signals in the generated ACT are assumed to be hazard-free. Furthermore:
+   * The ''bool'' ports are replaced with channels. By default, the ''e1of2'' channel from the ACT standard library is used. The channel type can be specified using the ''-C'' command line option.
+   * Signal fanout is replaced by an explicit templated channel ''copy'' process that is assumed to exist in an asynchronous library.
+   * The clock signal is eliminated from flip-flops. The assumption is that the asynchronous version of the flip-flop is an initial token buffer, which is in the asynchronous cell library. The name of the clock signal can be specified using the ''-c'' command-line option.
+Apart from these changes, the rest of the conversion proceeds in a similar fashion as the normal mode.