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| tools:v2act [2025/07/25 16:11] – [Standard import mode] rajit | tools:v2act [2025/07/25 16:22] (current) – [Async import mode] rajit |
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| (''v2act'' sanity checks ports, which is why this is required for translation.) | (''v2act'' sanity checks ports, which is why this is required for translation.) |
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| The ''actflow'' repository includes a tool called ''lib2act.py''. This is a program that can emit ACT cell declarations from a Synopsys Liberty (''.lib'') file. This is a hack, so it may not always work (i.e. it doesn't include a real Liberty file parser and makes certain assumptions about the text layout of the ''.lib'' file) but you may find it helpful as a starting point since these files are used by logic synthesis engines for cell mapping. For example, running | The ''actflow'' repository includes a tool called ''lib2act.py''. This is a program that can emit ACT cell declarations from a Synopsys Liberty (''.lib'') file. This is a hack, so it may not always work (i.e. it doesn't include a real Liberty file parser and makes certain assumptions about the text layout of the ''.lib'' file) but you may find it helpful as a starting point for creating an ACT cell library from a ''.lib'' file. For example, running |
| <code> | <code> |
| $ lib2act.py < osu018_stdcells.lib | $ lib2act.py < osu018_stdcells.lib |
| </code> | </code> |
| where the ''.lib'' file is the OSU 180nm open-source Liberty file provided by OSU results in the following output: | where ''osu018_stdcells.lib'' file is the 180nm open-source Liberty file provided by OSU results in the following output: |
| <code> | <code> |
| export defcell AND2X1 (bool? A, B; bool! Y); | export defcell AND2X1 (bool? A, B; bool! Y); |
| ===== Async import mode ===== | ===== Async import mode ===== |
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| In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the ''-a'' option. | In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the ''-a'' option. In this mode, by default, all signals in the generated ACT are assumed to be hazard-free. Furthermore: |
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| | * The ''bool'' ports are replaced with channels. By default, the ''e1of2'' channel from the ACT standard library is used. The channel type can be specified using the ''-C'' command line option. |
| | * Signal fanout is replaced by an explicit templated channel ''copy'' process that is assumed to exist in an asynchronous library. |
| | * The clock signal is eliminated from flip-flops. The assumption is that the asynchronous version of the flip-flop is an initial token buffer, which is in the asynchronous cell library. The name of the clock signal can be specified using the ''-c'' command-line option. |
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| | Apart from these changes, the rest of the conversion proceeds in a similar fashion as the normal mode. |