Differences

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--- tools:v2act [2025/07/25 16:12] – [Standard import mode] rajit
+++ tools:v2act [2025/07/25 16:22] (current) – [Async import mode] rajit
@@ Line 80: / Line 80: @@
 $ lib2act.py < osu018_stdcells.lib
 </code>
-where the ''.lib'' file is the OSU 180nm open-source Liberty file provided by OSU results in the following output:
+where ''osu018_stdcells.lib'' file is the 180nm open-source Liberty file provided by OSU results in the following output:
 <code>
 export defcell AND2X1 (bool? A, B; bool! Y);
@@ Line 118: / Line 118: @@
 ===== Async import mode =====
-In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the ''-a'' option.
+In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the ''-a'' option. In this mode, by default, all signals in the generated ACT are assumed to be hazard-free. Furthermore:
+   * The ''bool'' ports are replaced with channels. By default, the ''e1of2'' channel from the ACT standard library is used. The channel type can be specified using the ''-C'' command line option.
+   * Signal fanout is replaced by an explicit templated channel ''copy'' process that is assumed to exist in an asynchronous library.
+   * The clock signal is eliminated from flip-flops. The assumption is that the asynchronous version of the flip-flop is an initial token buffer, which is in the asynchronous cell library. The name of the clock signal can be specified using the ''-c'' command-line option.
+Apart from these changes, the rest of the conversion proceeds in a similar fashion as the normal mode.