Table of Contents

Layout configuration options

The layout configuration parameters have to be selected by examining the design rule manual for the technology of interest. Since these parameters tend to be covered by NDAs, the ones provided below are for illustration purposes only and don't correspond to any real technology (they are roughly similar to the scalable CMOS rules).

Note that the layout.conf file is treated specially: all parameters within it are assumed to be within a begin layout/end block.

General parameters

begin info
  string name "scmos"
  string date "Created on Feb 26, 2018 by Rajit Manohar"
end

This is a simple information section to provide some information about the design rules and which technology they are for. Note that the name field should be a string without any whitespace characters. 

begin general
  real scale 300           # rules use 300nm as one unit
  int metals 3             # three metal layers
  int dummy_poly 0         # dummy poly
  int welltap_adjust 0     # welltap adjustment
end

The scale factor converts the units in the file to nanometers. The number of metals is specified in this section as well. Additionally, a global parameter that specifies the number of dummy polys needed when drawing transistors is also included in this section.

welltap_adjust is a special parameter used in the generation of welltap cells. In some technologies, the well contact for n-type devices has to be moved down relative to its default generation. The welltap_adjust is set to the distance the contact for n-type transistor has to be moved down relative to its default location.

Range tables

Simple drawing rules for a material can be specified using minimum width and minimum spacing rules. This used to be sufficient for older CMOS technologies. More modern technologies have more complex rules, that are of the form: `if some other dimension is in the range [a,b], then the minimum width/spacing/overhang is c'. This can be specified by a tuple (a,b,c). To specify rules of this type, we use integer range tables.

Tables of this type will have 2n+1 entries, where n is the number ranges to be specified, with the last entry being the value of c for all other ranges. To specify a collection rules of the type (a0,b0,c0), (b0+1,b1,c1), (b1+1,b2, c2), etc. we assume the ranges cover all possible values of the the 'other dimension.' This means that a0 is implicit—it is the minimum legal value (can be taken as zero if necessary). The table will be specified with entries b0, c0, b1, c1, b2, c2, etc.

For illustration purposes, we know that in some modern technologies, polysilicon overhang over diffusion can depend on the width of the polysilicon drawn. 

int_table overhang 8 4 12 6 8

This specifies that: for widths [0,8] the overhang is 4 units; for widths [9,12] the overhang is 6 units; for all other widths, the overhang is 8 units.

GDS Layers

Although ACT mostly deals with abstract geometry, eventually the design has to be converted into foundry-standard GDS format. To support this, the GDS section is used to specify GDS layer names and the GDS layer numbers for each GDS layer. This section can be omitted if you'd like to stop at abstract geometry, and convert your design to GDS using other mechanisms (e.g. through your own technology file for commercial tools or for open-source layout editors like magic). 

begin gds
  string_table layers "PO" "OD" "CO" "M1" "M2" "M3" 
  int_table major      1     2    3    4    5    6
  int_table minor      0     0    0    0    0    0
end

This specifies the GDS layer names using layers, and the corresponding major and minor layer number. When the gds section is specified, all material sections must provide two additional parameters:

For metal and via templates, the additional information is described in the template section.

Base layer material names

The next section specifies the names/types for various types of diffusion, transistors, wells, and substrate diffusion. 

begin diff
  string_table types "svt"          # only svt devices
  string_table ptype "pdiff"        # p diffusion
  string_table ntype "ndiff"        # n diffusion
  string_table pfet  "ptransistor"  # fets
  string_table pfet_well "nwell:nndiff"  # well for p-fet, and nplus diff
  string_table nfet  "ntransistor"  # fets
  string_table nfet_well ":ppdiff"  # no pwell, but pplus diff exists
end

The types table corresponds to the different types of transistors/diffusion, and hence has to match the dev_flavors table in the global ACT configuration. Each following table specifies the names of the layout layers in the order specified by the types table. For wells, each entry corresponds to the well name followed by a colon, and then followed by the substrate diffusion name. If the colon is omitted, the string corresponds to the well name. If there is no well or substrate diffusion, then the empty string can be used. The names nndiff and ppdiff are used to indicate nplus diffusion and pplus diffusion, and is only used to draw substrate (well) contacts.

Materials for transistors

The materials section contains all the information about the materials that the layout library uses. The names used for the different transistor types (specified in the diff section) are used in this section. In addition, there are built-in names for polysilicon and each metal layer (m followed by an integer starting from one). The foundry technology file contains information that can be used to map these abstract layers to the correct layer names. The concrete layers can be generated automatically from the abstract layers using simple mapping rules. The reason for doing this is to have a layout generator whose output file can be easily converted into an input for any layout editor. In the layout generator directory, we provide a sample translator that creates a magic script which can be used to draw all the generated layout in the magic VLSI layout editor.

For each diffusion type specified in the header, there must be an entry that corresponds to the rules used to draw the material. There are several parameters that can be specified, all integers. The entire set of parameters are specified within a begin/end section of the configuration file: 

begin materials
   begin pdiff
      # pdiff parameters go here
   end
   begin ndiff
      # ndiff parameters go here
   end
   begin ppdiff
      # ppdiff parameters go here
   end
   begin nndiff
      # nndiff parameters go here
   end
   begin ptransistor
      # ptransistor parameters go here
   end
   begin ntransistor
      # ntransistor parameters go here
   end
   begin nwell
      # nwell rules go here
   end
   begin polysilicon
      # polysilicon rules go here
   end
end

The illustrations below will follow the convention: Illustration convention

Diffusion

For each type of diffusion, the basic parameters to be specified are:

Diffusion design rules

Transistors

For each type of transistor, the basic parameters to be specified are:

Transistor design rules

Wells and ppdiff/nndiff

For each type of well, the basic parameters are:

Well design rules

For each type of nplus/pplus diffusion (nndiff and ppdiff), the basic parameters are:

Since nndiff/ppdiff is only drawn for well contacts, the entire region will be within the corresponding well.

nplus/pplus diffusion design rules

Polysilicon

All transistors are drawn by polysilicon intersecting with diffusion. The type of transistor is determined by the type of diffusion. Polysilicon is the one unusual layer in that it may also get used for routing, even though its primary purpose is to define transistors. The polysilicon section has:

Poly design rules

Metal layers

Metal layer rules are a subset of the rules used for polysilicon. Essentially they are similar except for the rules related to diffusion/transistors. Often a technology has many metal layers, but many of the layers have the same design rules. To support this common scenario, we specify metal layers using metal layer templates. Metal layers are referred to using m1, m2, etc. based on the total number of metal layers specified. 

begin materials
   begin metal
     begin 1x
       # rules for 1x metal go here
     end
     begin 2x
       # rules for 2x metal go here
     end

     string m1 "1x"
     string m2 "1x"
     string m3 "2x"
   end
end

The items within the metal specification are:

Two additional parameters can be specified, which are used during LEF generation for automated routing.

Metal design rules

The example below shows how to specify GDS layer names and bloat for metal 1. 

  string m1 "1x"
  string_table m1_gds "GDS" "LAYER" "NAME" "LIST"
  int_table m1_gds_bloat 0 0 0 0

When magic technology files are auto-generted from layout.conf, the standard naming conventions in magic are used (e.g. m1 = first metal layer, m2 = second metal layer, etc). When generating LEF/DEF, it is advisable to use the technology layer names used by the foundry. 

string m1_lefname "FoundryM1Name"

This will use FoundryM1Name in the LEF output produced for cells, even though the magic layout layer name will remain m1.

Vias

When the layout generator draws a contact between two layers, it consists of a via plus the two layers being connected. Each layer is drawn using the minimum via surround rules. One of the complexities of drawing contacts is that this minimal amount of material by itself may not satisfy the design rule constraints, because each material might have minimum area rules, and contacts might have asymmetric material surround requirements.

There are two basic types of contacts: symmetric and asymmetric contacts. Both have a minimum via surround requirement in terms of the materials they connect. In symmetric contacts, that is sufficient to create the contact. In asymmetric contacts, you also need a larger minimum surround on two opposite sides of the contact. Technologies sometimes support both contact types, although the layout generator currently supports only using one of the two contact types.

Like metal layers, via rules are similar for many different supported vias; hence, vias are also specified using templates as follows: 

begin vias
   begin ct_to_active
   # rules for drawing connections to active here
   end
   begin via_small
   # rules for small  vias
   end
   begin via_large
   # rules for large vias
   end
   
   string polysilicon "ct_to_active"
   string polysilicon_name "gc"
   string ndiff "ct_to_active"
   string ndiff_name "gc"
   string pdiff "ct_to_active"
   string pdiff_name "gc"
   # maps for diff/transistor/well/select go here

   string m1 "via_small"
   string m1_name "v1"
   string m1_dstyle "via1arrow"
   string m2 "via_large"
   string m2_name "v2"
   string m2_dstyle "via2"
end

There are three sets of strings associated with each via

A via implicitly has a lower and upper layer that it connects. A via template contains the following rules:

Via design rules

The example below shows how to specify GDS information for the m1 via 

   string_table m1_gds "V1" "OTHER" "LAYERS"
   int_table m1_gds_bloat 0 0 0