Tools

In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow.

• actsim: an ACT simulator.
• prs2net: a production rule to SPICE netlist generator
• prs2sim: a production rule to sim file converter
• ext2sp: converts magic extract files into a hierarchical spice file
• Layout generation
• lvp: layout versus production rules
• act2lef: Generate LEF/DEF from an ACT design
• act2v: Convert ACT file into a Verilog netlist
• adepend: Print dependencies of an ACT file
• chp2prs: convert CHP to production rules
• interact: Interactive ACT
• prs2cells: extract ACT cells needed to implement a design
• v2act: Translate a Verilog netlist into an ACT file
• xcell: Cell library characterizer

These are core ACT tools–i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT command-line arguments, in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.

Standalone tools:

• prsim: a digital production-rule simulator
• aflat and prspack: a production rule flattener and compaction tool. See the documentation for prsim.
• AMC: an asynchronous memory compiler

External open-source tools:

• Xyce: An analog circuit simulator developed by Sandia National Labs
• magic: The Magic VLSI layout editor
• irsim: A switch-level circuit simulator
• Layout versus schematic (LVS) checking:
  • Gemini: a netlist comparison for strict layout-versus-schematic checking Gemini
  • netgen: another tool for LVS

Two useful concepts to keep in mind when using the ACT tools are expanded names and mangled names.