Tools

In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow.

The tools are in two categories:

1. The core ACT tools–i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT command-line arguments, in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.
2. A few tools (marked with (old)) do not either because they will, over time, be replaced by ACT tools or because their functionality is independent of the ACT library.

Two useful concepts to keep in mind when using the ACT tools are expanded names and mangled names.

We use a combination of our own simulators as well as other open-source simulators to verify functionality of our circuits.

• actsim: an ACT simulator.
• prsim: a digital production-rule simulator (old)
• Third-party tools:
  • Xyce: An analog circuit simulator developed by Sandia National Labs. Note that actsim can also be linked against the Xyce library as part of its build process to provide mixed-mode simulation.
  • irsim: A switch-level circuit simulator

Different VLSI tools use different file formats, and we provide a number of tools to convert between a range of file formats. These can be used to, for example, generate industry-standard formats from ACT or to import third-party designs into ACT.

• prs2net: a production rule to SPICE netlist generator
• prs2sim: a production rule to sim file converter
• ext2sp: converts magic extract files into a hierarchical spice file
• act2lef: Generate LEF/DEF from an ACT design
• act2v: Convert ACT file into a Verilog netlist. Note this is only useful for converting netlists in ACT format to Verilog format; the Verilog itself is structural, and doesn't contain translations of language bodies.
• v2act: Translate a Verilog netlist into an ACT file
• aflat and prspack: a production rule flattener and compaction tool. See the documentation for prsim. (old)

These are tools that are useful for translating ACT files into a final implementation in GDS, as well as verifying different aspects of the design.

• interact: Interactive ACT: this is the main tool for the ACT flow. It includes enough functionality to implement many of the standalone tools, including prs2cells, prs2net, prs2sim, act2v, and act2lef. In addition, it is used for the ACT ASIC flow.
• Layout generation
• lvp: layout versus production rules
• chp2prs: convert CHP to production rules
• prs2cells: extract ACT cells needed to implement a design
• xcell: Cell library characterizer
• AMC: an asynchronous memory compiler (old)
• FPGA mapping: tools to translate ACT into a simulation model for prototyping on standard FPGAs.

Third-party tools:

• magic: The Magic VLSI layout editor
• Gemini: a netlist comparison for strict layout-versus-schematic checking Gemini
• netgen: another tool for LVS

The following utilities are also provided as part of the core ACT repository:

• pgen: a parser generator used to emit the ACT parser. Used internally.
• adepend: Print dependencies of an ACT file suitable for use in a Makefile