The ACT VLSI design tools

Log In

Trace:

You are here: start » asic

Old Revisions

These are the older revisons of the current document. To revert to an old revision, select it from below, click Edit this page and save it.

2026/05/10 12:04 asic:start – [Logic synthesis] rajit +2 B (current)
2026/05/10 12:03 asic:start – [Logic synthesis] rajit -123 B
2026/05/10 12:02 asic:start – [Logic synthesis] rajit +651 B
2023/11/23 17:14 asic:start – rajit -386 B
2023/11/23 17:06 asic:start – rajit -2.8 KB
2023/11/23 17:05 asic:start – [Physical Implementation] rajit -31 B
2023/11/23 17:04 asic:start – rajit -7.6 KB
2023/11/23 16:59 asic:start – [Physical Implementation] rajit +103 B
2023/11/23 16:59 asic:start – rajit +381 B
2023/11/18 20:40 asic:start – [Timing analysis] rajit +50 B
2023/11/18 17:12 asic:start – [Cell libraries] rajit +12 B
2023/11/17 21:12 asic:start – [Timing analysis] rajit +22 B
2023/11/17 21:12 asic:start – [Timing analysis] rajit +259 B
2023/11/17 20:48 asic:start – [Placement and routing] rajit +187 B
2023/11/17 20:46 asic:start – [Timing and power analysis] rajit +16 B
2023/07/08 16:26 asic:start – [Logic synthesis] rajit +132 B
2023/07/08 16:10 asic:start – [Cell physical design] rajit +1 B
2023/07/08 16:09 asic:start – [Cell physical design] rajit +8 B
2023/07/07 20:04 asic:start – [Placement and routing] rajit +12 B
2023/07/07 19:41 asic:start – [Placement and routing] rajit +2 B

asic/start.txt · Last modified: 2026/05/10 12:04 by rajit

Except where otherwise noted, content on this wiki is licensed under the following license: GNU Free Documentation License 1.3