Differences

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--- asic:timing:graph [2024/03/22 15:11]
rajit [Why tick edges at all?]
+++ asic:timing:graph [2024/03/29 06:19]
rajit [How does one tick edges?]
@@ Line 11: / Line 11: @@
 {{ :asic:timing:invring2.png?200 | inverter ring}}
-What happens if we make one of the ring oscillators slower? The C-element will wait for the //slower// of the two oscillators before changing its output. Hence, the cycle period of this particular circuit will be determined by the slowest cycle of gates in the circuit. This simple example and intuition can be translated into a [[https://csl.yale.edu/~rajit/abstracts/exactmulti.html|rigorous mathematical framework]], where we can show that an asynchronous circuit will exhibit periodic behavior.((S.M. Burns and A.J. Martin. Performance Analysis and Optimization of Asynchronous Circuits. Proc. ARVLSI, 1991.))((Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018.))
+What happens if we make one of the ring oscillators slower? The C-element will wait for the //slower// of the two oscillators before changing its output. Hence, the cycle period of this particular circuit will be determined by the slowest cycle of gates in the circuit. This simple example and intuition can be translated into a [[https://csl.yale.edu/~rajit/abstracts/exactmulti.html|rigorous mathematical framework]], where we can show that an asynchronous circuit will exhibit periodic behavior((S.M. Burns and A.J. Martin. Performance Analysis and Optimization of Asynchronous Circuits. Proc. ARVLSI, 1991.))((Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018.)) and that the period is determined by the //slowest// cycle of gates that oscillate.
 ===== From gates to events =====
@@ Line 58: / Line 58: @@
 In the examples above, it was clear where the ticks in the timing graph should be placed. However, in a general asynchronous circuit, determining the placement of ticks after-the-fact is a non-trivial problem.
-In fact, techniques for doing this that are known (e.g. described in the Cyclone paper)  have a computational complexity that is comparable to logic synthesis. Also, they use information that is in fact computed during logic synthesis of asynchronous circuits! Hence, the ACT flow assumes that tick placement is computed and generated during the logic synthesis process. These tick specifiers are included in the [[language:langs:spec|''spec'' sub-language]].
+In fact, techniques for doing this that are known (e.g. described in the Cyclone paper)  have a computational complexity that is comparable to state-space exploration. Also, they use information that is in fact computed during logic synthesis of asynchronous circuits! Hence, the ACT flow assumes that tick placement is computed and generated during the logic synthesis process. These tick specifiers are included in the [[language:langs:spec|''spec'' sub-language]].
 Placing ticks in the right location is probably the most confusing aspect of building a correct timing graph for asynchronous circuits. What follows are some rules of thumb that should help you with this process. Note that if you are using our logic synthesis tools, they automatically tick the appropriate edges in the timing graph, so this section need not concern you. However, if you are generating your own asynchronous design via some alternate approach, then you will need to develop a strategy for ticking the appropriate edges in the timing graph.