Differences

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--- config:netlist [2022/07/10 15:17]
rajit [LEF/DEF configuration options]
+++ config:netlist [2024/03/31 13:44] (current)
rajit [Device generation and parameters]
@@ Line 100: / Line 100: @@
 <code>
-real unit_cap 1e-15
+real unit_dev 1e-15
 </code>
-This value is used to specify the size of the unit capacitor used for explicit capacitors specified in the ''prs'' sublanguage. If unspecified, it is taken to be 1fF.
+This value is used to specify the size of the unit device parameter used for explicit devices specified in the ''prs'' sublanguage. If unspecified, it is taken to be 10<sup>-15</sup>. This is normally used for capacitors.
 <code>
 real delay 500e-12
 </code>
-This parameter is used to convert delay units specified in timing constraints to actual time (in seconds).
+This parameter is used to convert delay units specified in timing constraints to actual time (in seconds). If unspecified, this is taken to be ''lambda'' divided by thousand, which is the standard rule of thumb for FO4 delay (assuming that ''lambda'' is half the feature size).
 <code>
@@ Line 115: / Line 114: @@
 In some process technologies, the foundry-provided model files include a global scale factor that applies to all width/length parameters. As a result, the netlist output generated for SPICE simulation have to be
 scaled to counteract the global scale factor. ''output_scale_factor'' is used to scale the output of all width/length/area/perimeter values; the width and length are multiplied by this scale factor only when printing the SPICE output.
+<code>
+int emit_parasitics 0
+</code>
+This option is used to generate parasitic source/drain area and perimeter values for transistors. For netlists suitable for running LVS checks, this setting should be off (0). Depending on how parasitics are extracted in a particular process technology (e.g. are source/drain caps part of the model, or are they explicitly extracted), this parameter should be set to 1 (turn on area/perimeter values) or 0.
+The netlist pass can be used to generate a [[https://csl.yale.edu/~rajit/ps/shared_stat_2020.pdf|shared staticizer]] structure. In this mode, one can specify that minimum and maximum number of staticizers that are permitted for a single shared weak power supply terminal.
+<code>
+int_table weak_sharing 2 8
+</code>
+This specifies that the sharing count for a weak supply is between two and eight staticizers.
 ===== Transistor device names =====
@@ Line 160: / Line 173: @@
 </code>
 The default is blank, but it can be changed as necessary.
+===== Other Devices =====
+Since ''prs'' bodies can have other two-terminal devices, the string to be used in the SPICE output for the device
+can be specified as:
+<code>
+string_table device "C"
+</code>
+This says the first device in the ''prs_device'' table is a capacitor (since ''C'' is the device string used by SPICE for capacitors).
 ===== Interactions with the layout editor Magic =====
@@ Line 205: / Line 228: @@
 </code>
 When production rules are automatically mapped to cells by the cell mapping pass, cell names are generated based on the production rule expressions for the pull-up and pull-down network. These names can get very long, and be difficult to read. This table is used to translate a generated name into something that is more understandable. The table should have an even number of entries that alternate between the generated name and the mapped name.
+<code>
+string cell_inport "in"
+string cell_outport "out"
+</code>
+When cells are generated, their ports are called ''in'' and ''out''. This can be changed to any port name using these configuration file options.
 ====== Sizing configuration options ======