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2024/03/26 06:14
history:start
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rajit
-4 B
2024/03/22 16:06
asic:timing:start
– [Creating the timing graph]
rajit
+37 B
2024/03/22 15:11
asic:timing:graph
– [Why tick edges at all?]
rajit
+14 B
2024/03/21 14:14
asic:timing:upcontrol.png
– created
rajit
+9.3 KB
2024/03/21 14:12
asic:timing:upfull.png
– created
rajit
+11.6 KB
2024/03/21 13:36
asic:timing:constraints
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rajit
+612 B
2024/03/21 12:46
asic:timing:tick_eg1b.png
– created
rajit
+10.4 KB
2024/03/21 12:46
asic:timing:tick_eg1a.png
– created
rajit
+11 KB
2024/03/20 07:19
language:expressions
– [External circuit functions]
rajit
+4 B
2024/03/13 09:50
intro_example:cadence_import
– [Example: FIFO boolean buffer]
ifx_async
-5 B
2023/11/18 07:38
asic:timing:invrer.png
– created
rajit
+3.4 KB
2023/11/18 07:29
asic:timing:inver.png
– created
rajit
+4.7 KB
2023/11/18 07:21
asic:timing:invtrans2.png
– created
rajit
+6.6 KB
2023/11/18 07:21
asic:timing:invtrans.png
– created
rajit
+3.4 KB
2023/11/18 07:08
asic:timing:invring2.png
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rajit
+538 B
2023/11/18 07:08
asic:timing:invring.png
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rajit
+485 B
2022/06/21 09:03
summer2022:21_customdesign.pdf
– created
rajit
+616.7 KB
2022/06/20 16:20
summer2022:flow.eg.tgz
– created
rajit
+969.9 KB
2022/06/20 16:19
summer2022:cell.eg.tgz
– created
rajit
+3.8 KB
2022/06/20 16:19
summer2022:timing.eg.tgz
– created
rajit
+1 KB
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