magic, irsim, yosys, and Xyce (Xyce installed using a Github repo that includes dependencies), and SPICE models and an irsim parameter file for the Skywater 130 open-source PDK.This is an old revision of the document!
ASYNC 2024 Summer School
Welcome to the ASYNC 2024 Summer School! This is the second summer school on asynchronous design. We will be following the format of the ASYNC 2022 Summer School, with videos and slides posted online.
(If the video is not visible when you click on the link, try downloading the file and viewing it locally. The videos play on the open-source VLC player, for example.)
Design tools
We have pre-installed tools in a multi-platform Docker image (linux/arm64 and linux/amd64) using Ubuntu Linux that is accessible through docker hub. The standard way we use this image is detailed here. You can also install the ACT tools from source using the instructions on Github.1)
An additional tool used in Week 3 is Workcraft. Packages for Workcraft are available on Github, with additional documentation available as well.
Week 1 : Behavioral design
Monday, July 1, 9:00AM to 1:00PM Eastern Time
| Time | Topic | Speaker(s) | Video |
|---|---|---|---|
| 9:00 AM | Welcome | Ivan Sutherland | mp4 |
| 9:10 AM | Overview of summer school + introduction to async | Rajit Manohar | mp4 mp4 |
| 9:40 AM | break | ||
| 9:45 AM | Message-passing behavioral description | Rajit Manohar | mp4 |
| 10:45 AM | Examples: CHP simulation | Rajit Manohar | mp4 |
| 11:00 AM | Dataflow design: pipelined circuits and performance estimation | Montek Singh | mp4 |
| 11:45 AM | Examples: simulating dataflow models | Rajit Manohar | mp4 |
| 12:00 PM | From dataflow to circuits | Montek Singh | mp4 |
| 1:00 PM | End of day | ||
Additional resources
Some additional links to resources that are relevant for the first day:
Reference materials:
- Introduction to Asynchronous Design, by Jens Sparsø. A freely available textbook.
Week 2: Gate-level design
Monday, July 8, 9:00AM to 1:00PM Eastern Time
| Time | Topic | Speaker(s) | Video |
|---|---|---|---|
| 9:00 AM | Recap of models; handshake protocols | Rajit Manohar | |
| 9:50 AM | break | ||
| 10:00 AM | Gates and gate-level simulation | Rajit Manohar | |
| 10:25 AM | break | ||
| 10:30 AM | Pipeline example | Rajit Manohar | |
| 11:00 AM | break | ||
| 11:10 AM | Syntax-directed translation to cells | Rajit Manohar | |
| 12:15 PM | Non-determinism and a simple clocked interface | Rajit Manohar | |
| 12:45 PM | Q&A | ||
| 1:00 PM | End of day | ||
Week 3: Physical design
Monday, July 15, 9:00AM to 1:00PM Eastern Time
| Time | Topic | Speaker | Video |
|---|---|---|---|
| 9:00 AM | Recap | Rajit Manohar | |
| 9:05 AM | Introduction to Petri Nets | Alex Yakovlev | |
| 10:00 AM | Controller synthesis using Petri Nets | Alex Yakovlev | |
| 10:55 AM | break | ||
| 11:00 AM | Custom circuit design | Benjamin Hill | |
| 11:55 AM | break | ||
| 12:00 PM | Using commercial tools: standard cell flow | Ole Richter | |
| 12:30 PM | Integration with a mixed-signal flow | Filip Hormot | |
| 12:45 PM | Q&A | all | |
1)
In addition to the ACT tools, the docker image includes binaries for