Verilog netlist to ACT

The v2act tool can be used to translate a Verilog netlist into ACT format. This program is used internally by the ACT expression optimization library to invoke third-party logic synthesis tools and incorporate their output back into an ACT design. It has been tested against Verilog netlists generated by Synopsys design compiler, Cadence's Genus, yosys, and abc.

The usage for v2act is summarized by:

Usage: v2act [act-options] [-a] [-n lib_namespace] [-c clkname] [-o outfile] -l <lib> <file.v>
  -a : async output
  -g : toggle hazard generation
  -C <chan>: change default channel name to <chan>
  -c <clkname>: specifies the clock port name [default: clock]
  -o <file> : specify output file name [default: stdout]
  -l <lib>  : synchronous library (act file) [default: sync.act]
  -n <ns>   : look for library components in namespace <ns>

This is the normal usage for v2act, and is what occurs when the -a option is not specified. In this mode, the Verilog netlist is assumed to be a collection of gate-level instances from a cell library. For error checking, v2act requires an ACT file that contains the library description. To understand how this works, here is a simple example of a Verilog netlist:

test.v

module testv (in, out);
  input in;
  output out;
  INVX2 i0(.A(in),.Y(out));
endmodule

To convert this Verilog netlist into ACT, we need an ACT cell library that defines INVX2. Ideally you would have a complete cell definition (including production rules, sizing, etc.) for the cells needed, but you can also use a black box definition. A cell library that includes just this gate would be:

cell.act

namespace cell {
 
defcell INVX2 (bool? A; bool! Y) {
  prs {
     A => Y-
  }
  sizing {  Y {-2} }
}
} 

The Verilog netlist can be translated into ACT using:

$ v2act -n cell -l cell.act test.v

This will generate:

/* -- declarations -- */
export defproc testv (bool? in; bool! out);
 
export defproc testv (bool? in; bool! out)
{
  spec { hazard(*) }
 
   /*--- types ---*/
   cell::INVX2 i0;
   /*--- connections ---*/
   i0(.A=in, .Y=out);
}

In this usage, the clocked design in the Verilog netlist is converted to a gate-level pipelined asynchronous implementation. To activate this mode, use the -a option.