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tools:actsim [2023/04/14 14:52] rajit [Example with a test environment] |
tools:actsim [2023/04/16 11:32] (current) rajit [Using files for test data] |
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} | } | ||
</ | </ | ||
+ | |||
+ | ==== Direct environment in ACT ==== | ||
A simple test environment would look like this: | A simple test environment would look like this: | ||
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Running '' | Running '' | ||
- | Since this is a commonly-used approach, the [[stdlib: | + | Since this is a commonly-used approach, the [[stdlib: |
+ | |||
+ | ==== Using pre-defined sources and sinks with data in the ACT file ==== | ||
+ | |||
+ | The same example can be written using the helper processes provided as follows: | ||
<file act testadd2.act> | <file act testadd2.act> | ||
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adder a; | adder a; | ||
sim:: | sim:: | ||
- | | + | |
- | 3, // three data values | + | 3, // three data values |
- | {3, | + | {3, |
- | > s1(a.A); | + | > s1(a.A); |
sim:: | sim:: | ||
sim:: | sim:: | ||
- | | + | |
- | > sx(a.C); | + | > sx(a.C); |
} | } | ||
</ | </ | ||
+ | |||
+ | ==== Using files for test data ==== | ||
Instead of providing the data values in the ACT test environment, | Instead of providing the data values in the ACT test environment, | ||
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sim:: | sim:: | ||
sim:: | sim:: | ||
- | | + | |
- | > sx(a.C); | + | > sx(a.C); |
} | } | ||
</ | </ | ||
+ | |||
+ | This example will also need a file '' | ||
===== Mixed-signal simulations ===== | ===== Mixed-signal simulations ===== | ||
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===== Configuration file ===== | ===== Configuration file ===== | ||
+ | An ACT configuration file can be read into '' | ||
+ | |||
+ | |||
+ | ==== CHP configuration options ==== | ||
+ | |||
+ | < | ||
+ | begin sim | ||
+ | begin chp | ||
+ | int inf_loop_opt 0 | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | '' | ||
+ | |||
+ | < | ||
+ | begin sim | ||
+ | begin chp | ||
+ | int default_delay 0 | ||
+ | real default_leakage 0 | ||
+ | int default_area 0 | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | These set default simulation parameters for CHP processes. The default delay sets the value for each non-skip basic statement (send, receive, assignment) in a CHP program. The default leakage per process can be secified (in nW), as can the default area (in square microns). | ||
+ | |||
+ | < | ||
+ | begin sim | ||
+ | begin chp | ||
+ | int debug_metrics 0 | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | If this is set to 1, then debugging messages are printed out showing the metrics that '' | ||
+ | |||
+ | ==== Mixed-signal simulation ==== | ||
+ | |||
+ | The mixed-signal simulation parameters are used to configure the interface to Xyce, and are contained in a sim.device block. | ||
+ | < | ||
+ | begin sim | ||
+ | begin device | ||
+ | # put mixed-signal parameters here | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | The parameters are | ||
+ | < | ||
+ | real timescale 1e-12 | ||
+ | </ | ||
+ | This is used for the time resolution of the Xyce output trace files, if any. | ||
+ | |||
+ | < | ||
+ | real analog_window 0.05 | ||
+ | </ | ||
+ | This specifies when an analog signal output should be treated as a digital 0 or digital 1. The value 0.05 means within 5% of the rail-to-rail voltage. So for a 1V power supply, this would be 0.95 for a digital 1 threshold, and 0.05 for a digital 0 threshold. | ||
+ | |||
+ | < | ||
+ | int case_for_sim 1 | ||
+ | </ | ||
+ | SPICE is case-insensitive, | ||
+ | |||
+ | < | ||
+ | real settling_time 1e-12 | ||
+ | </ | ||
+ | This is the settling time parameter for the built-in ADC device used to convert between the digital and analog signals. | ||
+ | |||
+ | < | ||
+ | int dump_all 1 | ||
+ | </ | ||
+ | If this is true, all voltage signals should be saved to the output trace file. Otherwise, only the interface signals are saved to the trace file. | ||
+ | |||
+ | < | ||
+ | string output_format " | ||
+ | </ | ||
+ | This specifies which output trace file formats should be generated from the underlying analog simulation engine. Any number of colon-separated formats are supported, but only one of the built-in formats (raw, prn, etc) can be used. | ||
+ | |||
+ | < | ||
+ | int waveform_steps 10 | ||
+ | real waveform_time 10e-12 | ||
+ | </ | ||
+ | The digital input is converted to a ramp before being fed to the analog simulation. This specifies the duration and number of steps used for the conversion. | ||
+ | |||
+ | < | ||
+ | string model_files " | ||
+ | </ | ||
+ | By default, the simulation will look for the file '' | ||
+ | |||
+ | < | ||
+ | string outfile " | ||
+ | </ | ||
+ | This is the name of the trace file output that is generated. | ||
+ | |||
+ | < | ||
+ | real stop_time 100e-12 | ||
+ | </ | ||
+ | This is the time at which the trace file output should stop. | ||
+ | |||
+ | ==== Standard sim namespace helper functions ==== | ||
+ | |||
+ | The standard simulation library (in the sim namespace) uses a few configuration file settings to pick the names | ||
+ | of the files for I/O. | ||
+ | |||
+ | < | ||
+ | begin sim | ||
+ | begin file | ||
+ | string prefix " | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | Change this parameter to modify the default file names used by the file I/O library used by the standard simulation namespace. | ||
+ | |||
+ | Alternatively, | ||
+ | < | ||
+ | begin sim | ||
+ | begin file | ||
+ | string_table name_table " | ||
+ | end | ||
+ | end | ||
+ | </ | ||
+ | If this parameter is specified, then the prefix parameter is ignored. | ||