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tools:actsim [2023/04/14 14:57]
rajit [Using pre-defined sources and sinks with data in the ACT file]
tools:actsim [2023/04/16 11:32] (current)
rajit [Using files for test data]
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  }  }
 </file> </file>
 +
 +==== Using files for test data ====
  
 Instead of providing the data values in the ACT test environment, you can instead have data values read in from a file. ''sim::file_source'' can be used for this purpose as follows: Instead of providing the data values in the ACT test environment, you can instead have data values read in from a file. ''sim::file_source'' can be used for this purpose as follows:
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     sim::source_seq<32, false, 3, {7,9,3}> s2(a.B);     sim::source_seq<32, false, 3, {7,9,3}> s2(a.B);
     sim::sink<true, // log output     sim::sink<true, // log output
-                        32  // 32-bit +              32  // 32-bit 
-                        > sx(a.C);+              > sx(a.C);
  }  }
 </file> </file>
 +
 +This example will also need a file ''_infile_.0'' that contains the [[sim:start|list of values]].
 ===== Mixed-signal simulations ===== ===== Mixed-signal simulations =====
  
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 ===== Configuration file ===== ===== Configuration file =====
  
 +An ACT configuration file can be read into ''actsim'' to control its behavior. The following summarizes configuration options that affect the behavior of the simulator (beyond the default ACT configurations that affect all tools). The simulator loads in the default ''actsim.conf'' file, but any of those parameters can be augmented/over-ridden using the ''-cnf'' [[stdoptions:start|command-line option]].
 +
 +
 +==== CHP configuration options ====
 +
 +<code>
 +begin sim
 +  begin chp
 +    int inf_loop_opt 0
 +  end
 +end
 +</code>
 +''actsim'' can detect an infinite loop where no state changes occur, and delete the process from the simulation environment if this flag is turned on (by being set to 1).
 +
 +<code>
 +begin sim
 +  begin chp
 +    int default_delay 0
 +    real default_leakage 0
 +    int default_area 0
 +  end
 +end
 +</code>
 +These set default simulation parameters for CHP processes. The default delay sets the value for each non-skip basic statement (send, receive, assignment) in a CHP program. The default leakage per process can be secified (in nW), as can the default area (in square microns).
 +
 +<code>
 +begin sim
 +  begin chp
 +    int debug_metrics 0
 +  end
 +end
 +</code>
 +If this is set to 1, then debugging messages are printed out showing the metrics that ''actsim'' was looking for in the configuration file, and what metrics were in fact found.
 +
 +==== Mixed-signal simulation ====
 +
 +The mixed-signal simulation parameters are used to configure the interface to Xyce, and are contained in a sim.device block.
 +<code>
 +begin sim
 +  begin device
 +    # put mixed-signal parameters here  
 +  end
 +end
 +</code>
 +The parameters are
 +<code>
 +real timescale 1e-12  
 +</code>
 +This is used for the time resolution of the Xyce output trace files, if any.
 +
 +<code>
 +real analog_window 0.05
 +</code>
 +This specifies when an analog signal output should be treated as a digital 0 or digital 1.  The value 0.05 means within 5% of the rail-to-rail voltage. So for a 1V power supply, this would be 0.95 for a digital 1 threshold, and 0.05 for a digital 0 threshold.
 +
 +<code>
 +int case_for_sim 1
 +</code>
 +SPICE is case-insensitive, and the internals of the analog simulator usually have either a lowercase or uppercase name for all the signals. Set this to 1 (the default, and correct value for Xyce) if it is uppercase, 0 for lowercase.
 +
 +<code>
 +real settling_time 1e-12
 +</code>
 +This is the settling time parameter for the built-in ADC device used to convert between the digital and analog signals.
 +
 +<code>
 +int dump_all 1
 +</code>
 +If this is true, all voltage signals should be saved to the output trace file. Otherwise, only the interface signals are saved to the trace file.
 +
 +<code>
 +string output_format "prn:lxt2:alint:vcd"
 +</code>
 +This specifies which output trace file formats should be generated from the underlying analog simulation engine. Any number of colon-separated formats are supported, but only one of the built-in formats (raw, prn, etc) can be used.
 +
 +<code>
 +int waveform_steps 10
 +real waveform_time 10e-12
 +</code>
 +The digital input is converted to a ramp before being fed to the analog simulation. This specifies the duration and number of steps used for the conversion.
 +
 +<code>
 +string model_files "path.sp"
 +</code>
 +By default, the simulation will look for the file ''models.sp'' in the ACT configuration directory. This string can be used to override this default and pick a different SPICE file that includes all the needed models.
 +
 +<code>
 +string outfile "xyce_out"
 +</code>
 +This is the name of the trace file output that is generated.
 +
 +<code>
 +real stop_time 100e-12
 +</code>
 +This is the time at which the trace file output should stop.
 +
 +==== Standard sim namespace helper functions ====
 +
 +The standard simulation library (in the sim namespace) uses a few configuration file settings to pick the names
 +of the files for I/O. 
 +
 +<code>
 +begin sim
 +  begin file
 +    string prefix "_infile_"
 +  end
 +end
 +</code>
 +Change this parameter to modify the default file names used by the file I/O library used by the standard simulation namespace.
 +
 +Alternatively, a file name table can be specified whose entries are the names of the files to be used for each file ID (0 = first entry, 1 = second entry, etc.)
 +<code>
 +begin sim
 +  begin file
 +    string_table name_table "file1.in" "file2.in"
 +  end
 +end
 +</code>
 +If this parameter is specified, then the prefix parameter is ignored.