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--- tools:actsim [2023/04/14 15:26]
rajit [Standard sim namespace helper functions]
+++ tools:actsim [2023/04/16 11:32] (current)
rajit [Using files for test data]
@@ Line 303: / Line 303: @@
  }
 </file>
+This example will also need a file ''_infile_.0'' that contains the [[sim:start|list of values]].
 ===== Mixed-signal simulations =====
@@ Line 320: / Line 322: @@
 ==== CHP configuration options ====
+<code>
+begin sim
+  begin chp
+    int inf_loop_opt 0
+  end
+end
+</code>
+''actsim'' can detect an infinite loop where no state changes occur, and delete the process from the simulation environment if this flag is turned on (by being set to 1).
+<code>
+begin sim
+  begin chp
+    int default_delay 0
+    real default_leakage 0
+    int default_area 0
+  end
+end
+</code>
+These set default simulation parameters for CHP processes. The default delay sets the value for each non-skip basic statement (send, receive, assignment) in a CHP program. The default leakage per process can be secified (in nW), as can the default area (in square microns).
 <code>
-int sim.chp.inf_loop_opt 0
+begin sim
+  begin chp
+    int debug_metrics 0
+  end
+end
 </code>
-''actsim'' can detect an infinite loop where no state changes occur, and delete the process from the simulation environment if this flag is turned on (by being set to 1).
+If this is set to 1, then debugging messages are printed out showing the metrics that ''actsim'' was looking for in the configuration file, and what metrics were in fact found.
+==== Mixed-signal simulation ====
+The mixed-signal simulation parameters are used to configure the interface to Xyce, and are contained in a sim.device block.
 <code>
-int sim.chp.default_delay 10
+begin sim
+  begin device
+    # put mixed-signal parameters here
+  end
+end
+</code>
+The parameters are
+<code>
+real timescale 1e-12
 </code>
-This is the default delay for each non-skip basic statement (send, receive, assignment) in a CHP program.
+This is used for the time resolution of the Xyce output trace files, if any.
 <code>
-int sim.chp.default_leakage 0
+real analog_window 0.05
 </code>
-This is the default leakage associated with a process (in nW)
+This specifies when an analog signal output should be treated as a digital 0 or digital 1.  The value 0.05 means within 5% of the rail-to-rail voltage. So for a 1V power supply, this would be 0.95 for a digital 1 threshold, and 0.05 for a digital 0 threshold.
 <code>
-int sim.chp.default_area 0
+int case_for_sim 1
 </code>
-This is the default area associated with a CHP process (square microns).
+SPICE is case-insensitive, and the internals of the analog simulator usually have either a lowercase or uppercase name for all the signals. Set this to 1 (the default, and correct value for Xyce) if it is uppercase, 0 for lowercase.
 <code>
-int sim.chp.debug_metrics 0
+real settling_time 1e-12
 </code>
-If this is set to 1, then debugging messages are printed out showing the metrics that ''actsim'' was looking for in the configuration file, and what metrics were in fact found.
+This is the settling time parameter for the built-in ADC device used to convert between the digital and analog signals.
+<code>
+int dump_all 1
+</code>
+If this is true, all voltage signals should be saved to the output trace file. Otherwise, only the interface signals are saved to the trace file.
+<code>
+string output_format "prn:lxt2:alint:vcd"
+</code>
+This specifies which output trace file formats should be generated from the underlying analog simulation engine. Any number of colon-separated formats are supported, but only one of the built-in formats (raw, prn, etc) can be used.
+<code>
+int waveform_steps 10
+real waveform_time 10e-12
+</code>
+The digital input is converted to a ramp before being fed to the analog simulation. This specifies the duration and number of steps used for the conversion.
+<code>
+string model_files "path.sp"
+</code>
+By default, the simulation will look for the file ''models.sp'' in the ACT configuration directory. This string can be used to override this default and pick a different SPICE file that includes all the needed models.
+<code>
+string outfile "xyce_out"
+</code>
+This is the name of the trace file output that is generated.
+<code>
+real stop_time 100e-12
+</code>
+This is the time at which the trace file output should stop.
 ==== Standard sim namespace helper functions ====
@@ Line 370: / Line 436: @@
 </code>
 If this parameter is specified, then the prefix parameter is ignored.
-==== Mixed-signal simulation ====
-sim.device.timescale
-sim.device.analog_window
-sim.device.case_for_sim
-sim.device.settling_time
-sim.device.dump_all
-sim.device.output_format
-sim.device.waveform_steps
-sim.device.waveform_time
-sim.device.model_files
-sim.device.outfile
-sim.device.stop_time