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tools:actsim [2023/04/14 15:33] rajit [Mixed-signal simulation] |
tools:actsim [2023/04/16 11:32] (current) rajit [Using files for test data] |
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} | } | ||
</ | </ | ||
+ | |||
+ | This example will also need a file '' | ||
===== Mixed-signal simulations ===== | ===== Mixed-signal simulations ===== | ||
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< | < | ||
- | sim.device.analog_window | + | real analog_window |
- | sim.device.case_for_sim | + | |
- | sim.device.settling_time | + | |
- | sim.device.dump_all | + | |
- | sim.device.output_format | + | |
- | sim.device.waveform_steps | + | |
- | sim.device.waveform_time | + | |
- | sim.device.model_files | + | |
- | sim.device.outfile | + | |
- | sim.device.stop_time | + | |
</ | </ | ||
+ | This specifies when an analog signal output should be treated as a digital 0 or digital 1. The value 0.05 means within 5% of the rail-to-rail voltage. So for a 1V power supply, this would be 0.95 for a digital 1 threshold, and 0.05 for a digital 0 threshold. | ||
+ | < | ||
+ | int case_for_sim 1 | ||
+ | </ | ||
+ | SPICE is case-insensitive, | ||
+ | |||
+ | < | ||
+ | real settling_time 1e-12 | ||
+ | </ | ||
+ | This is the settling time parameter for the built-in ADC device used to convert between the digital and analog signals. | ||
+ | |||
+ | < | ||
+ | int dump_all 1 | ||
+ | </ | ||
+ | If this is true, all voltage signals should be saved to the output trace file. Otherwise, only the interface signals are saved to the trace file. | ||
+ | |||
+ | < | ||
+ | string output_format " | ||
+ | </ | ||
+ | This specifies which output trace file formats should be generated from the underlying analog simulation engine. Any number of colon-separated formats are supported, but only one of the built-in formats (raw, prn, etc) can be used. | ||
+ | |||
+ | < | ||
+ | int waveform_steps 10 | ||
+ | real waveform_time 10e-12 | ||
+ | </ | ||
+ | The digital input is converted to a ramp before being fed to the analog simulation. This specifies the duration and number of steps used for the conversion. | ||
+ | |||
+ | < | ||
+ | string model_files " | ||
+ | </ | ||
+ | By default, the simulation will look for the file '' | ||
+ | |||
+ | < | ||
+ | string outfile " | ||
+ | </ | ||
+ | This is the name of the trace file output that is generated. | ||
+ | |||
+ | < | ||
+ | real stop_time 100e-12 | ||
+ | </ | ||
+ | This is the time at which the trace file output should stop. | ||
==== Standard sim namespace helper functions ==== | ==== Standard sim namespace helper functions ==== |