Lab 1: Introduction to Layout and Simulation

Goal. The goal of this lab is to complete your first abstract layout of a digital circuit, and simulate it to verify its functionality using both a switch-level simulator as well as a circuit simulator.

Most of the work for this lab will involve becoming familiar with the layout tool we will be using (called magic) by completing some of the tutorials provided with the software package.

  $ echo $ACT_HOME
  /usr/local/cad/

Please read and complete the following tutorials:

• Tutorial 1: Getting Started
• Tutorial 2: Basic Painting and Selection
• Tutorial 6: Design rule checking
• Tutorial 8: Circuit Extraction
• Tutorial 4: Cell Hierarchies

All files needed for the tutorial are available

Additional documentation about the magic VLSI layout editor can also be found online.

We will be using the original MOSIS scalable CMOS design rules for deep submicron feature sizes (pdf). These rules are suitable for use with the TSMC 0.18μm fabrication technology, even though they are more conservative to preserve the λ rules abstraction.

A bit more info: Most manufacturing technologies have proprietary design rules, and accessing them requires signing non-disclosure agreements. Using λ rules may incur some overhead, but it keeps the layout more portable. Currently there are a small number of open-source technologies with public design rules. These include Skywater 130nm, Global Foundries 180nm, and iHP 130nm. The detailed design rules and manufacturing technology information is provided in a process design kit (or PDK).

To use this technology file with magic, start magic with the -T command-line option, like the following:

$ magic -T SCN6M_DEEP.09

• pdiffusion (or pdiff) to indicate p-type material
• ndiffusion (or ndiff) to indicate n-type material
• polysilicon (or poly) to indicate polysilicon. When this overlaps with diffusion, a transistor is created
• pdc (short for pdiffusion contact), to connect pdiff to metal1
• ndc (short for ndiffusion contact), to connect ndiff to metal1
• pwell and nwell for wells.
• nsc and psc for n-substrate contacts and p-substrate contacts to connect to the wells.
• pc (short for poly contact), to connect poly to metal1
• m1 (short for metal1), to draw wires
• m2c to connect metal1 to metal2
• m2 (short for metal2) to draw wires

The technology also supports more layers of metal, which you should not use for this lab.

magic is an open-source tool, and uses the tcl/tk open-source library for graphics. The magic console uses the TkCon package, and colors can be configured by creating a .tkconrc file in your home directory. An example is below:

set ::tkcon::COLOR(bg) ivory
set ::tkcon::OPT(font) "{Liberation Mono} 10"

Draw an inverter.

• Save the layout in file inv.mag
• Label the power supplies Vdd! and GND!
• Label the primary input in, and the primary output out
• Make sure the layout is design-rule check (DRC) clean (no white dots)
• Make sure you have drawn both the P-well and N-well layers, and have also drawn the P-substrate contact and N-substrate contact and connected them to the appropriate power supply.

Simulate your layout to verify its functionality. The first step is to extract the layout---i.e. to convert the geometry into a representation of the devices in the layout (resistors, capacitors, transistors, etc.). The magic tutorial covers how to do this. Extract the layout to create inv.ext

Switch-level simulation. Within magic, create a simulation file using

:ext2sim alias on
:ext2sim

Simulate the inverter using the irsim simulation environment. To run irsim, use

$ irsim g180 inv.sim inv.al

This starts the simulation environment, uses simulation parameters from the file g180.prm (stored in a standard location), and reads in the .sim file just created.

There are irsim tutorials online. For the inverter chain, if your primary input is called in and the primary output is called out, you can run a simple simulation by the following sequence of irsim commands:

% ana in out

% h Vdd!
% l GND!

% s

You can also create a text file of irsim commands (highly recommended as a general practice), and then read it in to irsim with the @ command. Create a script inv.irsim corresponding to the irsim commands that you used to verify the functionality of your inverter.

Analog/circuit-level simulation. We will now simulate the inverter using a low-level circuit simulator that contains a much more detailed model of the transistors. The simulator is called Xyce, and is an open-source implementation provided by Sandia National Labs. Its input format is SPICE, because the file format is based on the input used by one of the earliest circuit simulators (called spice). One "exciting" thing is that that the SPICE format is case-insensitive, so if you have a signal labeled in and another signal labeled In, they will be treated as the same signal in Xyce...

Convert the inv.ext file into a spice file by using the command:

$ ext2sp -Tg180 inv.ext > inv.spice

A template spice file is provided. The file contains a test harness. It includes the technology library (line .inc ...) and test.spice, and sets the input to the inverter using a piece-wise linear waveform. Look at the commands within test.sp so that you understand how the file works. (* is a comment specifier in the spice format). Create a spice test file inv_test.sp based on test.sp, and run a circuit simulation using:

$ Xyce inv_test.sp

For the test example, you can view the waveform with the following gnuplot commands:

$ gnuplot

gnuplot>set style data lines
gnuplot>plot 'test.plot' using ($2*1e9):3 title 'v(in)', 'test.plot' using ($2*1e9):4 title 'v(out)'

Verify that the circuit behaves as expected. Save the waveform plot for your inverter as a PDF file (inv_test.pdf).

Repeat this process for:

• A two-input NAND gate (nand2.mag)
• A two-input NOR gate (nor2.mag)

• A 4-input OR gate (or4.mag)
• An 8-input OR gate (or8.mag)

For your simulation setup, make sure you try a few different input combinations to verify the functionality of your logic.

• Your layout (inv.mag, nand2.mag, nor2.mag, or4.mag, or8.mag)
• Your irsim scripts that contain what you ran (inv.irsim, nand2.irism, etc...)
• Your SPICE test harness fiels that contain your test (inv_test.sp, nand2_test.sp, etc.)
• PDF plots showing the output of your Xyce simulation (inv_test.pdf, nand2_test.pdf, etc.)
• A one-page PDF (lab.pdf) that summarizes what you did for this lab. For each gate, include a picture of the layout.
  • To generate a picture, place the box over your layout and then use the magic command `:plot pnm file'
  • This creates file.pnm that contains a picture of your layout. pnm is an open-source file format, and you can convert it to most other file formats using freely available tools.
• Measure the bounding box in lambda, and the area in lambda^2 units, and report this in your lab writeup.