Lab 2: Combinational Logic

Goal. The goal of this lab is to implement a set of commonly used combinational logic blocks using restoring logic.

For each computational block described below, you have to do the following:

• Write down production rules for the block, that describes the pull-up and pull-down networks to be used. Note that you can decide to use multiple stages of logic, use additional inverters, etc. as you see fit.
• Convert the production rules into the transistor-level implementation.
• Layout the transistor level implementation using magic.
• Simulate your circuit using irsim to verify its functionality.

The three computational blocks you have to implement for this lab are:

1. A function block that can compute an arbitrary two-input/one-output Boolean function.
   • This block takes two one-bit inputs a and b, and four other inputs g0, g1, g2, and g3.
   • The output of the block is f.
   • The values of g0-g3 correspond to the truth table for the function.
   In other words, the output f is equal to g0 when a=0,b=0, f=g1 when a=0,b=1, etc. For example, this block could be used to implement an AND gate by setting g0=0, g1=0, g2=0, g3=1---the truth table for the AND gate, and using a and b as primary inputs and f as the output. (A function block can be used to implement any two-input Boolean function.)
2. An add/subtract unit.
   • The inputs are a, b, and the carry-in cin.
   • The output is s (the sum) and cout (carry-out).
3. An up/down shift unit.
   • This unit takes three inputs a, ad, and au, and additional control inputs s (0 if the output should not be shifted, 1 if the output should be shifted), and u (1 if the output is shifted up, 0 if the output is shifted down), and produces output o.
   • When s=0, the output o should be a; when s=1, if u=1, then the output should be au; otherwise the output should be ad.

Use the magic :array command to create an 8-bit array that implements 8-bit versions of the three functions. You may need some additional circuitry/wiring to finish the layout.

1. For the function block, all 8-bits use the same four control signals g0-g3. The 8-bit block takes two 8-bit inputs a0..a7 and b0..b7, and produces a single 8-bit output f0..f7.
2. For the adder/subtract unit, the final 8-bit block will have a single carry-in and a single carry-out, and the carry chain should be connected internally. If the carry-in to the adder is 1, then the block should perform a subtraction; if the carry-in to the adder is 0, then the block should perform an addition. In other words, the carry-in to the 8-bit unit is used to also serve as the control that determines if the block performs an addition or subtraction.
3. For the up/down shift unit, the block takes a single 8-bit input a0..a7, and two control inputs s and u that are shared by all the 8 blocks. Wire up the inputs so that if s=0, the output o0..o7 is a0..a7; when s=1, the output should be either o0=a1, o1=a2, etc and o7=0 when u=0, and o0=0, o1=a0, o2=a1, etc. when u=1.

(In the numbering convention above, bit 0 is the least significant bit of the number and bit 7 is the most significant bit.)

For this part, your design should use arrayable layout. In other words, make sure that most connections/etc for your layout are taken care of by simply abutting the layout for the individual bits.

For this lab, turn in a zip file that contains:

• Your layout
  • fblock_one.mag, addsub_one.mag, shift_one.mag (for part 1)
  • fblock.mag, addsub.mag, shift.mag (for part 2)
  • If you use sub-cells, make sure they are included in your zip file. The .mag files listed above are the "top-level" magic files for your layout
• The six corresponding irsim scripts that contains what you used to verify the functionality of your design
• A PDF that summarizes what you did for this lab. The document should contain three parts (one per computation block), and each part should have:
  • A one-page summary that contains
    • A picture of your layout (just the 8-bit version).
    • The maximum delay through the logic per irsim
    • The area of your layout (in lambda units)
  • An additional page (or multiple pages if you need them) that provide
    • The production rules you used for the one-bit block
    • The transistor-level implementation used
    • A description of any optimizations you might have used in the transistor-level implementation.