Lab 4: Putting it all together: control + datapath

Goal. The goal of this lab is to add a control state machine to Lab 3.

The input/output data signals are the in0..7 and out0..7 signals from your lab3 datapath. Let x be the contents of register 0, and y be the contents of register 1. The circuit must generate a single output control signal ready. When ready is a 1, this means that the output data on out corresponds to the value stored in x, and the circuit is ready to accept the next input command (on the cycle where ready goes high). Note that this means that ready must go high as soon as the circuit comes out of reset. The input control signals are:

• [input] reset: used to initialize the control and datapath
• [input] load: set to 1 for a load operation, 0 otherwise. When load is set to a 1, x is cleared (set to all zeros) and y is set to the value on the in bus.
• [input] iter: set to 1 for a "step" operation, 0 otherwise. When iter is high, the circuit updates x with the value (x<<1)^y. (^ denotes XOR.)

In addition to these signals, your finite state machine has to control all the datapath signals so that the datapath performs the appropriate operations. Follow the following convention for the datapath operation:

• Any operation that writes to the wz bus happens on phi1;
• Any operation that reads from the rx or ry buses happens on phi0;
• You can AND control signals with phi0 or phi1 to ensure this behavior.

Design a finite state machine that implements the operations outlined above. Assume that input signals from the external world will be stable on clock phase phi0.

• Provide a text description of the strategy used for controlling your datapath with a finite state machine. Detail what happens on each phase of the clock and how the control signals perform the appropriate datapath update operations to implement the required functionality.
• Draw the finite state machine, and specify the state assignment used.
• Draw the combinational logic used for the control signals, as well as latches labelled with the appropriate clock phase.

Complete the layout for your finite state machine, and wire it up to your datapath.

• Simulate the design in irsim, and check that it does what you expect. IRSIM has support for clocks, so you can do something like the following to simplify clock generation:

  vector CLOCK phi0 phi1
  clock CLOCK 00 10 00 01
  

  The c command will step through one clock cycle, and the p command will step through one clock phase. Note that the clock definition above is a two-phase non-overlapping clock.
• Provide a reasonable number of test cases to verify that your design operates as expected.

For this lab, turn in a zip file that contains:

• Your layout
• The design document for part 1
• A one-page PDF that summarizes what you did for this lab
  • A picture of your layout (just the 8-bit version).
  • The clock period for your design
  • The area of your layout (in lambda units)
• A separate PDF containing your project proposal. This must contain:
  • Description. An informal description of your proposed project
  • Signal list. A list of input/output signals. Describe each signal and what it represents
  • Components. Describe the major components that comprise your circuit. This includes what the storage requirements are, what datapath blocks you require, what the control requirements are, etc
  • Floorplan. You have roughly 3000 by 3000 lambda for your design. Determine approximate sizes for all the parts in the previous section and how you are going to place them on the chip
• The only constraint is that your layout should fit within 3500 lambda by 3500 lambda, and can have 40 input/output signals. Note that these signals include Vdd!, GND!, any reset signals you need, and clock(s). We require that you reserve 2 pins for the clock, 2 for power, 2 for ground, and 1 for reset